System Test Register (Sd_Systest); System Test Register (Sd_Systest) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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9.4.7 System Test Register (SD_SYSTEST)

This register is used to control the signals that connect to I/O pins when the module is configured in
system test (SYSTEST) mode for boundary connectivity verification.
NOTE: In SYSTEST mode, a write into SD_CMD register will not start a transfer. The buffer
behaves as a stack accessible only by the local host (push and pop operations). In this
mode, the Transfer Block Size (SD_BLK[10:0] BLEN bits) and the Blocks count for current
transfer (SD_BLK[31:16] NBLK bits) are needed to generate a Buffer write ready interrupt
(SD_STAT[4] BWR bit) or a Buffer read ready interrupt (SD_STAT[5] BRR bit) and DMA
requests if enabled.
The system test register (SD_SYSTEST) is shown in
31
15 14
SDCD SDWP
R/W-0 R/W-0
7 6
D3D D2D
R/W-0 R/W-0
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
Table 9-17. System Test Register (SD_SYSTEST) Field Descriptions
Bit Field Value
31-17 Reserved
16 OBI
15 SDCD
14 SDWP
13 WAKD
Read 0
Write 0
Read 1
Write 1
12 SSB
Read 0
Write 0
Read 1
Write 1
SPRUGX9 – 15 April 2011
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Preliminary
Figure 9-35. System Test Register (SD_SYSTEST)
Reserved
R-0
13 12
WAKD SSB
R/W-0 R/W-0
5 4
D1D D0D
R/W-0 R/W-0
Description
0 Reserved bit field. Do not write any value. Reads return 0.
Out-of-band interrupt (OBI) data value.
0 The out-of-band interrupt pin is driven low.
1 The out-of-band interrupt pin is driven high.
Card detect input signal (SDCD) data value
0 The card detect pin is driven low.
1 The card detect pin is driven high.
Write protect input signal (SDWP) data value
0 The write protect pin SDWP is driven low.
1 he write protect pin SDWP is driven high.
Wake request output signal data value
No action. Returns 0.
The pin SWAKEUP is driven low.
No action. Returns 1.
The pin SWAKEUP is driven high.
Set status bit. This bit must be cleared prior attempting to clear a status bit of the interrupt status
register (SD_STAT).
No action. Returns 0.
Clear this SSB bit field. Writing 0 does not clear already set status bits.
No action. Returns 1.
Force to 1 all status bits of the interrupt status register (SD_STAT) only if the corresponding bit
field in the Interrupt signal enable register (SD_ISE) is set.
© 2011, Texas Instruments Incorporated
Figure 9-35 and described in
11 10
D7D D6D
R/W-0 R/W-0
3 2
DDIR CDAT
R/W-0 R/W-0
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Registers
Table 9-17.
17 16
OBI
R/W-0
9 8
D5D D4D
R/W-0 R/W-0
1 0
CDIR MCKD
R/W-0 R/W-0
967