Test Register (Testr); Test Register (Testr) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

16.4.17 Test Register (TESTR)

The test register (TESTR) is used to put the SATASS slave interface into a test mode and to select a
Port for BIST operation.
The TESTR register is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field Value
31-19 Reserved 0
18-16 PSEL 0
15-1 Reserved 0
0 TEST_IF
0
1
1608
Serial ATA (SATA) Controller
Preliminary
Figure 16-18 and described in
Figure 16-18. Test Register (TESTR)
Reserved
R-0
Reserved
R-0
Table 16-20. Test Register (TESTR) Field Descriptions
Description
Reserved.
Port Select. Selects the port for BIST operation. Note that there are two ports in this subsystem, so 0
and 1 are valid values.
Reserved.
Test Interface. Places the DWC SATA AHCI slave interface into the test mode.
Normal mode: the read back value of some registers is a function of the DWC SATA AHCI state and
does not match the value written.
Test mode: the read back value of the registers matches the value written. Normal operation is
disabled. The following registers are accessed in this mode:
• GHC register: IE bit
• BISTAFR register: NCP and PD bits become read/write
• BISTCR register: LLC, ERREN, FLIP, PV, PATTERN
• BISTFCTR, BISTSR, BISTDECR registers become read/write
• P#CLB (# = 0 or 1)/CLBU, P#FB (# = 0 or 1)/FBU registers
• P#IS (# = 0 or 1) register: RW1C and UFS bits become read/write
• P#IE (# = 0 or 1) register
• P#CMD (# = 0 or 1) register: ASP, ALPE, DLAE, ATAPI, PMA bits
• P#TFD (# = 0 or 1), P#SIG (# = 0 or 1) registers become read/write
• P#SCTL (# = 0 or 1) register
• P#SERR (# = 0 or 1) register: R/W1C bits become read/write bits
• P#SACT (# = 0 or 1), P#CI (# = 0 or 1), P#SNTF (# = 0 or 1) registers become read/write
• P#DMACR (# = 0 or 1) register
• P#PHYCR (# = 0 or 1) register
• P#PHYSR (# = 0 or 1) register becomes read/write
Notes:
Where # = Port 0 or Port 1 above, the PSEL field will select the Port Number under test.
Interrupt is asserted if any of the IS register bits is set after setting the corresponding P0IS and P0IE
registers and GHC.IE = 1.
CAP.SMPS/SSS, PI, P0CMD.ESP/CPD/MPSP/ HPCP register bits are W/RO (written once after
power-on reset, then remain as read-only) type and can not be used in test mode.
Global DWC SATA AHCI reset must be issued (GHC.HR = 1) after TEST_IF bit is cleared following the
test mode operation.
© 2011, Texas Instruments Incorporated
Table 16-20.
19 18
SPRUGX9 – 15 April 2011
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16
PSEL
R/W-0
0
TEST_IF
R/W-0