Irq_Enable_Clr Register; Irq_Enable_Set Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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13.4.4.29 IRQ_ENABLE_SET Register
The interrupt enable set register (IRQ_ENABLE_SET is described in the figure and table below.
31
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set; -n = value after reset
Bit Field
31-4 Reserved
3 INTD
2 INTC
1 INTB
0 INTA

13.4.4.30 IRQ_ENABLE_CLR Register

The interrupt enable clear register (IRQ_ENABLE_CLR) is described in the figure and table below.
31
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Bit Field
31-4 Reserved
3 INTD
2 INTC
1 INTB
0 INTA
SPRUGX9 – 15 April 2011
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Preliminary
Figure 13-41. IRQ_ENABLE_SET Register
4
R-0
Table 13-44. IRQ_ENABLE_SET Register Field Descriptions
Value Description
0 Reserved
0 Legacy Interrupt D status. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt C status. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt B status. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt A status. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
Figure 13-42. IRQ_ENABLE_CLR Register
4
R-0
Table 13-45. IRQ_ENABLE_CLR Register Field Descriptions
Value Description
0 Reserved
0 Legacy Interrupt D disable. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt C disable. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt B disable. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
0 Legacy Interrupt A disable. Set to enable the interrupt. On read, one/zero means interrupt is
enabled/disabled.
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Reserved
R-0
3 2
INTD INTC
R/W1S-0 R/W1S-0
Reserved
R-0
3 2
INTD INTC
R/W1C-0 R/W1C-0
Peripheral Component Interconnect Express (PCIe)
Registers
8
1 0
INTB INTA
R/W1S-0 R/W1S-0
8
1 0
INTB INTA
R/W1C-0 R/W1C-0
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