Table of Contents
Advertisement
Registers
10.3.24 Transmitter Global Control Register (XGBLCTL)
Alias of the global control register (GBLCTL). Writing to the transmitter global control register
(XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value
of GBLCTL. XGBLCTL allows the transmitter to be reset independently from the receiver. The
XGBLCTL is shown in
description of GBLCTL.
31
15
Reserved
R-0
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-33. Transmitter Global Control Register (XGBLCTL) Field Descriptions
Bit
Field
Value
31-13
Reserved
0-FFh
12
XFRST
0
1
11
XSMRST
0
1
10
XSRCLR
0
1
9
XHCLKRST
0
1
8
XCLKRST
0
1
7-5
Reserved
0
4
RFRST
x
3
RSMRST
x
2
RSRCLR
x
1
RHCLKRST
x
0
RCLKRST
x
1102
Multichannel Audio Serial Port (McASP)
Preliminary
Figure 10-61
and described in
Figure 10-61. Transmitter Global Control Register (XGBLCTL)
13
12
XFRST
R/W-0
5
4
RFRST
R-0
Description
Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL.
Transmit frame sync generator is reset.
Transmit frame sync generator is active.
Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL.
Transmit state machine is held in reset.
Transmit state machine is released from reset.
Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL.
Transmit serializers are cleared.
Transmit serializers are active.
Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of
GBLCTL.
Transmit high-frequency clock divider is held in reset.
Transmit high-frequency clock divider is running.
Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL.
Transmit clock divider is held in reset.
Transmit clock divider is running.
Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of
GBLCTL. Writes have no effect.
Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL.
Writes have no effect.
Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes
have no effect.
Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value
of GBLCTL. Writes have no effect.
Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL.
Writes have no effect.
© 2011, Texas Instruments Incorporated
Table
10-33. See
Reserved
R-0
11
10
XSMRST
XSRCLR
R/W-0
R/W-0
3
2
RSMRST
RSRCLR
R-0
R-0
www.ti.com
Section 10.3.8
for a detailed
9
XHCLKRST
XCLKRST
R/W-0
R/W-0
1
RHCLKRST
RCLKRST
R-0
R-0
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
16
8
0
Advertisement
Table of Contents
