Transmit Bit Stream Format Register (Xfmt); Transmit Bit Stream Format Register (Xfmt) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

10.3.26 Transmit Bit Stream Format Register (XFMT)

The transmit bit stream format register (XFMT) configures the transmit data format. The XFMT is shown
in Figure 10-63 and described in
31
15 14 13
XRVRS XPAD
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-35. Transmit Bit Stream Format Register (XFMT) Field Descriptions
Bit Field Value
31-18 Reserved 0
17-16 XDATDLY 0-3h
0
1h
2h
3h
15 XRVRS
0
1
14-13 XPAD 0-3h
0
1h
2h
3h
12-8 XPBIT 0-1Fh
0
1-1Fh
1104
Multichannel Audio Serial Port (McASP)
Preliminary
Table 10-35.
Figure 10-63. Transmit Bit Stream Format Register (XFMT)
Reserved
R-0
12
XPBIT
R/W-0
Description
Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
Transmit sync bit delay.
0-bit delay. The first transmit data bit, AXRn, occurs in same ACLKX cycle as the transmit frame sync
(AFSX).
1-bit delay. The first transmit data bit, AXRn, occurs one ACLKX cycle after the transmit frame sync
(AFSX).
2-bit delay. The first transmit data bit, AXRn, occurs two ACLKX cycles after the transmit frame sync
(AFSX).
Reserved.
Transmit serial bitstream order.
Bitstream is LSB first. No bit reversal is performed in transmit format bit reverse unit.
Bitstream is MSB first. Bit reversal is performed in transmit format bit reverse unit.
Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits
when XMASK[n] = 0.
Pad extra bits with 0.
Pad extra bits with 1.
Pad extra bits with one of the bits from the word as specified by XPBIT bits.
Reserved.
XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra
bits before shifting. This field only applies when XPAD = 2h.
Pad with bit 0 value.
Pad with bit 1 to bit 31 value.
© 2011, Texas Instruments Incorporated
8 7
XSSZ
R/W-0
www.ti.com
18 17
XDATDLY
R/W-0
4 3 2
XBUSEL XROT
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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