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14.7.4.32 CM_SYSCLK24_CLKSEL Register
The CM_SYSCLK24_CLKSEL register selects the divider value for SYSCLK24. It is shown and
described in the figure and table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-64. CM_SYSCLK24_CLKSEL Register Field Descriptions
Bit
Field
31-3
Reserved
2-0
CLKSEL
SPRUGX9 – 15 April 2011
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Preliminary
Figure 14-49. CM_SYSCLK24_CLKSEL Register
Reserved
R-0
Value
Description
0
Reserved
Selects the divider value [warm reset insensitive]
0
Select SYS_CLK divided by 1
1h
Select SYS_CLK divided by 2
2h
Select SYS_CLK divided by 3
3h
Select SYS_CLK divided by 4
4h
Select SYS_CLK divided by 5
5h
Select SYS_CLK divided by 6
6h
Select SYS_CLK divided by 7
7h
Select SYS_CLK divided by 8
© 2011, Texas Instruments Incorporated
Power, Reset, and Clock Management (PRCM) Module
Registers
3
2
0
CLKSEL
R/W-0
1447
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