Cmd_Status Register; Cmd_Status Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.4.2 CMD_STATUS Register

The command status register (CMD_STATUS) is described in the figure and table below.
31
15
Reserved
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-12 Reserved
11-10 OCP_STANDBY
9-8 OCP_IDLE
7-6 Reserved
5 DBI_CS2
4 APP_RETRY_EN
3 POSTED_WR_EN
2 IB_XLT_EN
1 OB_XLT_EN
0 LTSSM_EN
1310
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-14. CMD_STATUS Register
12
R-0
5 4
DBI_CS2 APP_RETRY_EN
R/W-0 R/W-0
Table 13-17. CMD_STATUS Register Field Descriptions
Value Description
0 Reserved
0-3h OCP standby mode
0-3h OCP idle mode
0 Reserved
0 Set to enable writing to BAR mask registers that are overlaid on BAR registers.
0 Application Request Retry Enable—Setting this bit will enable all incoming PCIe transactions to
be returned with a retry response. This feature can be used if initialization can take longer than
PCIe stipulated time frame.
0 Posted Write Enable—Setting this bit will cause the OCP master to use posted write
commands. Default is zero with all OCP Master writes defaulting to non-posted.
0 Inbound Address Translation Enable—Setting this bit will enable translation of inbound
memory/io read/write requests into memory read/write requests.
0 Outbound Address Translation Enable—Setting this bit will enable translation of outbound
memory read/write requests into memory/io/cfg read/write requests.
0 Link Transitioning Enable—Setting this bit will enable LTSSM in PCI Express Core and link
negotiation with link partner will begin.
© 2011, Texas Instruments Incorporated
Reserved
R-0
11 10
OCP_STANDBY
R/W-2h
3
POSTED_WR_EN IB_XLT_EN
R/W-0 R/W-0
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9
OCP_IDLE
R/W-2h
2 1
OB_XLT_EN LTSSM_EN
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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16
8
0