Timer Synchronous Interface Control Register (Tsicr); Timer Capture Register (Tcar2); Timer Synchronous Interface Control Register (Tsicr) Field Descriptions; Timer Capture Register (Tcar2) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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17.3.16 Timer Synchronous Interface Control Register (TSICR)

Access to this register is not stalled even if the timer is in non-posted mode configuration. To abort any
wrong behavior, software can permanently reset the functional part of the module. Also in case of a
wrong hardware PIFREQRATIO tied the POSTED field can be reprogrammed on the fly, so deadlock
situation cannot happen.
NOTE: Reset value of POSTED depends on hardware integration module at design time.
Software must read POSTED field to get the hardware module configuration.
Figure 17-22. Timer Synchronous Interface Control Register (TSICR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-22. Timer Synchronous Interface Control Register (TSICR) Field Descriptions
Bit Field
31-3 Reserved
2 POSTED
1 SFT
0 Reserved

17.3.17 Timer Capture Register (TCAR2)

When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the
capture on second event is activated from the control register (TCLR), the current counter value is
stored to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer
clock, some synchronization is done in order to make sure that the TCAR2 value is not read while it is
being updated due to some capture event.
In 16-bit mode the following sequence must be followed to read the TCAR2 register properly:
• Perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2 register.
• Perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register.
31
LEGEND: R/W = Read/Write; -n = value after reset
Bit Field
31-0 CAPTURED_VALUE
SPRUGX9 – 15 April 2011
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Preliminary
Reserved
R-0
Value Description
0 Reserved
PIFREQRATIO
0 Posted mode inactive: will delay the command accept output signal.
1 Posted mode active (clocks ratio needs to fit freq (timer) < freq (OCP)/4 frequency requirement)
This bit resets all the function parts of the module. During reads it always returns 0.
0 Software reset is enabled
1 Software reset is disabled
0 Reserved
Figure 17-23. Timer Capture Register (TCAR2)
CAPTURED_VALUE
Table 17-23. Timer Capture Register (TCAR2) Field Descriptions
Value Description
0 Timer counter value captured on an external event trigger
© 2011, Texas Instruments Incorporated
R/W-0
Registers
3 2 1 0
POSTED SFT Reserved
R/W-0 R/W-0 R-0
Timers
0
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