Pm_Default_Pwrstst Register; Pm_Default_Pwrstst Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

14.7.9.2 PM_DEFAULT_PWRSTST Register

The PM_DEFAULT_PWRSTST register provides a status on the current DEFAULT power domain
state. [warm reset insensitive]. It is shown and described in the figure and table below.
31 21
Reserved INTRANSITION
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-89. PM_DEFAULT_PWRSTST Register Field Descriptions
Bit Field
31-21 Reserved
20 INTRANSITION
19-3 Reserved
2 LOGICSTATEST
1-0 POWERSTATEST
1472
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Figure 14-74. PM_DEFAULT_PWRSTST Register
20 19
Reserved
R-0 R-0
Value
0
0
1
0
0
1
0
1h
2h
3h
© 2011, Texas Instruments Incorporated
3
LOGICSTATEST
Description
Reserved
Domain transition status
No on-going transition on power domain
Power domain transition is in progress
Reserved
Logic state status
Logic in domain is OFF
Logic in domain is ON
Current power state status
OFF State
Reserved
Reserved
ON State
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2 1
POWERSTATEST
R-1 R-3h
SPRUGX9 – 15 April 2011
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