Ddc I2C Data Count Register (Ddc_Count1); Ddc I2C Data Count Register (Ddc_Count1) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

6.3.2.113 DDC I2C Data Count Register (DDC_COUNT1)

The DDC I2C data count register is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-144. DDC I2C Data Count Register (DDC_COUNT1) Field Descriptions
Bit Field
31-8 Reserved
7-0 DDC_COUNT
802
High-Definition Multimedia Interface (HDMI)
Preliminary
Figure 6-135. DDC I2C Data Count Register (DDC_COUNT1)
Reserved
R-0h
Description
Reserved
The total number of bytes to be read from the slave or written to the slave before a stop bit is sent on the
DDC bus. For example, if the HDCP KSV FIFO length is 635 bytes (127 devices x 5 bytes/KSV), the
DDC_COUNT must be 27Bh.
© 2011, Texas Instruments Incorporated
Figure 6-135 and described in
www.ti.com
Table 6-144.
8 7
DDC_COUNT1
R/W-0h
SPRUGX9 – 15 April 2011
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