I2C Registers - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
7.2.14.4 Initiate a Transfer
Poll the bus busy (BB) bit in the I2C status register (I2C_IRQSTATUS_RAW). If it is cleared to 0 (bus
not busy), configure START/STOP (I2C_CON: STT / I2C_CON: STP condition to initiate a transfer) -
only in case of I2C operating mode (F/S mode).
7.2.14.5 Receive Data
Poll the receive data ready interrupt flag bit (RRDY) in the I2C status register (I2C_IRQSTATUS_RAW),
use the RRDY interrupt (I2C_IRQENABLE_SET.RRDY_IE set) or use the DMA RX
(I2C_BUF.RDMA_EN set together with I2C_DMARXENABLE_SET) to read the receive data in the data
receive register (I2C_DATA). Use draining feature (I2C_IRQSTATUS_RAW.RDR enabled by
I2C_IRQENABLE_SET.RDR_IE)) if the transfer length is not equal with FIFO threshold.
7.2.14.6 Transmit Data
Poll the transmit data ready interrupt flag bit (XRDY) in the I2C status register
(I2C_IRQSTATUS_RAW), use the XRDY interrupt (I2C_IRQENABLE_SET.XRDY_IE set) or use the
DMA TX (I2C_BUF.XDMA_EN set together with I2C_DMATXENABLE_SET) to write data into the data
transmit register (I2C_DATA). Use draining feature (I2C_IRQSTATUS_RAW.XDR enabled by
I2C_IRQENABLE_SET.XDR_IE)) if the transfer length is not equal with FIFO threshold.
7.3 Registers
NOTE: All bits defined as reserved must be written by software with 0s, for preserving future
compatibility. When read, any reserved bit returns 0. Also, note that it is good software
practice to use complete mask patterns for setting or testing individually bit fields within a
register.
Address Offset Acronym
00h I2C_REVNB_LO
04h I2C_REVNB_HI
10h I2C_SYSC
20h I2C_EOI
24h I2C_IRQSTATUS_RAW
28h I2C_IRQSTATUS
2Ch I2C_IRQENABLE_SET
30h I2C_IRQENABLE_CLR
34h I2C_WE
38h I2C_DMARXENABLE_SET
3Ch I2C_DMATXENABLE_SET
40h I2C_DMARXENABLE_CLR
44h I2C_DMATXENABLE_CLR
48h I2C_DMARXWAKE_EN
4Ch I2C_DMATXWAKE_EN
90h 2C_SYSS
94h I2C_BUF
98h I2C_CNT
9Ch I2C_DATA
A4h I2C_CON
A8h I2C_OA
ACh I2C_SA
858 Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Table 7-3. I2C Registers
Register Name
Module Revision Register (LOW BYTES)
Module Revision Register (HIGH BYTES)
System Configuration Register
I2C End of Interrupt Register
I2C Status Raw Register
I2C Status Register
I2C Interrupt Enable Set Register
I2C Interrupt Enable Clear Register
I2C Wakeup Enable Register
Receive DMA Enable Set Register
Transmit DMA Enable Set Register
Receive DMA Enable Clear Register
Transmit DMA Enable Clear Register
Receive DMA Wakeup Register
Transmit DMA Wakeup Register
System Status Register
Buffer Configuration Register
Data Counter Register
Data Access Register
I2C Configuration Register
I2C Own Address Register
I2C Slave Address Register
© 2011, Texas Instruments Incorporated
www.ti.com
Section
Section 7.3.1
Section 7.3.2
Section 7.3.3
Section 7.3.4
Section 7.3.5
Section 7.3.6
Section 7.3.7
Section 7.3.8
Section 7.3.9
Section 7.3.10
Section 7.3.11
Section 7.3.12
Section 7.3.13
Section 7.3.14
Section 7.3.15
Section 7.3.16
Section 7.3.17
Section 7.3.18
Section 7.3.19
Section 7.3.20
Section 7.3.21
Section 7.3.22
SPRUGX9 – 15 April 2011
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