Overrun In The Mcbsp Receiver - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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11.2.3.1 Overrun in the Receiver
(ROVFLSTAT bit set to 1 in IRQSTATUS register, and legacy mode RFULL bit set to 1 in SPCR1_REG
register)
Indicates that the receiver has experienced overrun and is in an error condition. Receive overrun is set
when all of the following conditions are met:
• DRR_REG is not read even if the RRDY bit in IRQSTATUS register is set (legacy mode: RRDY bit
in SPCR1_REG register) and DMA or interrupt request has been asserted.
• RB is full
• RSR is full
As previously described, data arriving on McBSP.DR is continuously shifted into. Once a complete word
is shifted into the RSR, an RSR–to–RB copy can occur only if the RB is not full.
Either of the following events clears the legacy mode RFULL bit and allows subsequent transfers to be
read properly:
• The CPU or DMA controller reads DRR_REG.
• The receiver is reset individually (SPCR1_REG[0] register RRST bit = 0) or as part of an Global
reset.
Another frame–synchronization pulse is required to restart the receiver.
According to the IRQENABLE register setting, this condition can generate the COMMONIRQ line to be
asserted low. Writing 1 to the corresponding bit in status register will clear the interrupt.
Figure 11-14 shows the receive overrun condition.
CLKR
FSR
A1 A0
DR
RRDY
RFULL
SPRUGX9 – 15 April 2011
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Figure 11-14. Overrun in the McBSP Receiver
B5 B4 B3 B2
B7 B6
RB to DRR copy (A)
No read from DRR (A)
© 2011, Texas Instruments Incorporated
Preliminary
B1 B0
C7 C6
No read from DRR (B), RB full
Multichannel Buffered Serial Port (McBSP)
Architecture
C5 C4 C3 C2 C1
C0
RSR to RB copy (B)
Read from DRR (A)
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