Configuration Of Clocks Register (Hdmi_Wp_Clk); Configuration Of Clocks Register (Hdmi_Wp_Clk) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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6.3.1.9

Configuration of Clocks Register (HDMI_WP_CLK)

The configuration of clocks register is shown in
31
15
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-26. Configuration of Clocks Register (HDMI_WP_CLK) Field Descriptions
Bit Field
31-17 Reserved
16 OCP_TIME_OUT_DIS
15-6 Reserved
5-0 CEC_DIV
SPRUGX9 – 15 April 2011
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Preliminary
Figure 6-18. Configuration of Clocks Register (HDMI_WP_CLK)
Reserved
R-0
5
Value Description
0 Reserved
Timeout in case CEC_DDC_CLK not provided.
0 Timeout after 4095 OCP clock cycles after inactivity. HDMI Core register interface
(due to CEC_DDC_CLK not provided to HDMI). An interrupt is generated. No error
response is provided on the OCP interface.
1 No timeout capability
0 Reserved
Defines the divisor value to be used for the generation of the CEC clock (1MHz) from
the input CEC_DDC clock (48MHz). If 48 MHz is provided, the division by 24 is
required (18h) to get the expected CEC clock speed (2 MHz) The valid values are
from 0 to 63.
0 Gated
1 Free-running
© 2011, Texas Instruments Incorporated
Figure 6-18 and described in
Reserved
R-0
CEC_DIV
R/W
High-Definition Multimedia Interface (HDMI)
Registers
Table 6-26.
16
OCP_TIME_
OUT_DIS
R/W
8
0
729