Table of Contents
Advertisement
Architecture
19.2.6.4 IrDA Status FIFO
In IrDA modes, a status FIFO is used to record the received frame status. When a complete frame is
received, the length of the frame and the error bits associated with the frame are written into the status
FIFO. The frame length and error status can be read by reading SFREGL/H and SFLSR. Reading the
SFLSR causes the read pointer to be incremented. The status FIFO is eight entries deep and therefore
can hold the status of eight frames. The LH uses the frame-length information to locate the
frame-boundary in the received frame data. The LH can screen bad frames using the error-status
information and later request the sender to resend only the bad frames. This status FIFO can be used
very effectively in DMA as the LH need not be interrupted every time a frame is received but only
whenever the programmed status FIFO trigger level is reached.
19.2.6.5 Frame Closing
There are two ways by which a transmission-frame can be properly terminated:
•
Frame-length method: Frame-length method is selected when MDR1[7] = 0. The LH writes the
frame-length value to TXFLH and TXFLL registers. The device automatically attaches end flags to
the frame once the number of bytes transmitted becomes equal to the frame-length value.
•
Set-EOT bit Method: Set-EOT bit method is selected when MDR1[7] = 1. The LH writes 1 to
ACREG[0] (EOT bit) just before it writes the last byte to the TX FIFO. When the LH writes the last
byte to the TX FIFO, the device internally sets the tag bit for that particular character in the TX
FIFO. As the TX state machine reads data from the TX FIFO it uses this tag-bit information to attach
end flags and properly terminate the frame.
19.2.6.6 Store and Controlled Transmission (SCT)
In SCT the LH first starts writing data into the TX FIFO. Then, after it writes a part of a frame (for a
bigger frame) or a whole frame (a small frame, i.e. supervisory frame), it writes a 1 to ACREG[2]
(deferred TX start) to start transmission. SCT is enabled when MDR1[5] = 1. This method of
transmission is different from the normal mode, where transmission of data starts immediately after
data is written to the TX FIFO. SCT is useful to send short frames without TX underrun.
19.2.6.7 Underrun During Transmission
Underrun in transmission occurs when the TX FIFO becomes empty before the end of the frame is
transmitted. When underrun occurs, the device closes the frame with end-flags but attaches an
incorrect CRC value. The receiving device detects a CRC error and discards the frame; it can then ask
for a re-transmission. Underrun also causes an internal flag to be set which disables further
transmission. Before the next frame can be transmitted the system (LH) must:
•
Reset the TX FIFO
•
Read the RESUME register. This clears the internal flag.
This functionality can be disabled with ACREG[4], compensated by the extension of the stop bit in
transmission in case the TX FIFO is empty.
19.2.6.8 Overrun During Receive
Overrun occurs during receive if the RX state machine tries to write data into the RX FIFO when it is
already full. When overrun occurs, the device interrupts the LH with IIR[3] and discards the remaining
portion of the frame. Overrun also causes an internal flag to be set, which disables further reception.
Before the next frame can be received the system (LH) must:
•
Reset the RX FIFO
•
Read the RESUME register. This clears the internal flag.
1706
UART/IrDA/CIR Module
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
