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6.3.2.6
Software Reset Register (SRST)
The software reset register (SRST) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-2
Reserved
1
FIFORST
0
SWRST
6.3.2.7
System Control Register 1 (SYS_CTRL1)
The system control register 1 is shown in
31
15
7
6
Reserved
VSYNC
R-0h
R-Xh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-38. System Control Register 1 (SYS_CTRL1) Field Descriptions
Bit
Field
31-7
Reserved
6
VSYNC
5
VEN
4
HEN
SPRUGX9 – 15 April 2011
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Preliminary
Figure 6-28. Software Reset Register (SRST)
Reserved
R-0h
Table 6-37. Software Reset Register (SRST) Field Descriptions
Value
Description
0
Reserved
Audio FIFO reset
0
Normal operation
1
Reset (flush) audio FIFO
Software reset
0
Normal operation
1
Reset all sections, including audio FIFO but not writable registers or HDCP
Figure 6-29
Figure 6-29. System Control Register 1 (SYS_CTRL1)
5
4
VEN
HEN
R/W
R/W
Value
Description
0
Reserved
X
The current status of the VSYNC input pin. Refer to the INTR2 register for an interrupt tied to
VSYNC active edge.
VSYNC enable
0
Fixed LOW
1
Follow VSYNC input
HSYNC enable
0
Fixed LOW
1
Follow HSYNC input
© 2011, Texas Instruments Incorporated
Figure 6-28
and described in
Reserved
R-0h
and described in
Reserved
R-0h
Reserved
R-0h
3
2
Reserved
BSEL
R/W
R/W
High-Definition Multimedia Interface (HDMI)
Registers
Table
6-37.
2
1
FIFORST
SWRST
R/W
R/W
Table
6-38.
1
EDGE
R/W
R/W
16
0
16
8
0
PD
739
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