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Architecture
19.2.7.3 IrDA Mode Interrupts
In IrDA modes, there are eight possible interrupts. The interrupt line is activated when any of the eight
interrupts is generated (there is no priority). For IIR[5], interrupt source 1 is used with interrupt reset
method 1 and interrupt source 2 is used with interrupt reset method 2.
interrupt control functions.
IIR Bit
Interrupt Type
0
RHR interrupt
1
THR interrupt
2
Last byte in RX FIFO
3
RX overrun
4
Status FIFO interrupt
5
TX status
(indicated by MDR2[0]
(IRTX_UNDERRUN)
6
Receiver line status
interrupt
7
Received EOF
19.2.7.4 CIR Mode Interrupts
The CIR mode uses a subset of the existing IrDA mode interrupts.
modes that are to be maintained. In CIR mode, IIR bit 5 has a single purpose of indicating that the last
bit of infrared data has been passed to the IR TX pin.
IIR Bit
Interrupt Type
0
RHR interrupt
1
THR interrupt
2
RXSTOPIT interrupt
3
RXOEIT interrupt
4
N/A for CIR mode
5
TX status
6-7
N/A for CIR mode
1708 UART/IrDA/CIR Module
Preliminary
Table 19-5. IrDA Mode Interrupts
Interrupt Source
DRDY (data ready) (FIFO disable)
RX FIFO above trigger level (FIFO enable)
TFE (THR empty) (FIFO disable)
TX FIFO below trigger level (FIFO enable)
Last byte of frame in RX FIFO is available
to be read at the RHR port.
Write to RHR register when RX FIFO full.
Status FIFO triggers level reached.
1. THR empty before EOF sent. Last bit of 1. Read RESUME register.
transmission of the IrDA frame
occurred, but with an underrun error.
OR
2. Transmission of the last bit of the IrDA
frame completed successfully.
CRC, ABORT, or frame-length error is
written into STATUS FIFO.
Received end-of-frame.
Table 19-6. CIR Mode Interrupts
Interrupt Source
DRDY (data ready) (FIFO disable)
RX FIFO above trigger level (FIFO enable)
TFE (THR empty) (FIFO disable)
TX FIFO below trigger level (FIFO enable)
Receive stop interrupt (depending on value
set in the BOF length register (EBLR))
Write to RHR register when RX FIFO full.
Transmission of the last bit of the frame is
completed successfully.
© 2011, Texas Instruments Incorporated
Table 19-5
summarizes the
Interrupt Reset Method
Read RHR register until interrupt condition
disappears.
Write to THR register until interrupt
condition disappears.
Read RHR register.
Read RESUME register.
Read SFREGL/H, SFLSR. Status FIFO
read pointer is incremented only when
reading SFLSR.
OR
2. Read IIR register.
Read STATUS FIFO (read until empty -
maximum of eight reads required).
Read IIR register.
Table 19-6
summarizes the interrupt
Interrupt Reset Method
Read RHR register until interrupt condition
disappears.
Write to THR register until interrupt
condition disappears.
Read IIR register.
Read RESUME register.
Read IIR register.
SPRUGX9 – 15 April 2011
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