Bar1 Register; Busnum Register; Bar1 Register Field Descriptions; Busnum Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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13.4.7.3.1 BAR1 Register

The base address register 1(BAR1) is described in the figure and table below.
31
LEGEND: R = Read only; -n = value after reset
Bit Field
31-0 Base Address

13.4.7.4 BUSNUM Register

The latency timer and bus number register (BUSNUM) is described in the figure and table below.
31
Secondary Latency Timer
15
Secondary Bus Number
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-24 Secondary
Latency Timer
23-16 Subordinate Bus
Number
15-8 Secondary Bus
Number
7-0 Primary Bus
Number
SPRUGX9 – 15 April 2011
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Preliminary
Figure 13-94. BAR1 Register
Base Address
Table 13-100. BAR1 Register Field Descriptions
Value Description
0-FFFF FFFFh Base Address high 32 bits for BAR0. Actual writable bits are determined by BAR0
Mask Register.
Figure 13-95. BUSNUM Register
R-0
R/W-0
Table 13-101. BUSNUM Register Field Descriptions
Value Description
0-FFh Not applicable in PCI Express.
0-FFh Subordinate Bus Number. This is highest bus number on downstream interface.
0-FFh Secondary Bus Number. It is typically 1h for RC.
0-FFh Primary Bus Number. It is zero for RC and nonzero for switch devices only.
© 2011, Texas Instruments Incorporated
R-0
24 23
Subordinate Bus Number
8 7
Primary Bus Number
Peripheral Component Interconnect Express (PCIe)
Registers
R/W-0
R/W-0
0
16
0
1357