Compensation Illustration - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
The RTC_DISABLE bit of the CTRL register must only be used to completely disable the RTC function.
When this bit is set, the 32 kHz clock is gated, and the RTC is frozen. From this point, resetting this bit
to zero can lead to unexpected behavior. In order to save power, this bit should only be used if the RTC
function is unwanted in the application.
15.2.4.6 Crystal Compensation
To compensate for any inaccuracy of the 32 kHz oscillator, the ARM can perform a calibration of the
oscillator frequency, calculate the drift compensation versus one-hour period, and load the
compensation registers with the drift compensation value. Auto compensation is enabled by
AUTO_COMP_EN bit in the RTC_CTRL register. If the COMP_REG value is positive, compensation
occurs after the second change event. COMP_REG cycles are removed from the next second. If the
COMP_REG value is negative, compensation occurs before the second change event. COMP_REG
cycles are added to the current second. This enables compensation with a 1 32-kHz period accuracy
each hour. The waveform below summarizes positive and negative compensation effect.
Access to the COMP_MSB_REG and COMP_LSB_REG registers must respect the available access
period. These registers should not be updated during compensation (first second of each hour), but it is
alright to update them during the second preceding a compensation event. For example, the ARM could
load the compensation value into these registers after each hour event, during an available access
period.
Clk 32 kHz
Timer counter
Second update
Clk 32 kHz
Timer counter
Second update
Clk 32 kHz
Timer counter
Second update
1542
Real-Time Clock (RTC)
Preliminary
Figure 15-5. Compensation Illustration
7FFA 7FFB 7FFC 7FFD
Negative compensation: comp_reg = +2
7FFA 7FFB 7FFC 7FFD
Positive compensation: comp_reg = –2 (0xFFFE)
7FFA 7FFB 7FFC 7FFD
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No compensation
7FFE 7FFF 0000
7FFE 7FFF 0002
7FFE 7FFF 7FFE
2 cycles are added
to current second
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0001
0003
2 cycles are
removed from
next second
7FFF 0000
SPRUGX9 – 15 April 2011
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