Interrupt Unmask Register (Int_Unmask3) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
Table 6-117. Interrupt Unmask Register (INT_UNMASK3) Field Descriptions
Bit Field
31-8 Reserved
7 RI_ERR_3
6 RI_ERR_2
5 RI_ERR_1
4 RI_ERR_0
3 DDC_CMD_DONE DDC command is complete.
2 DDC_FIFO_HALF
1 DDC_FIFO_FULL
0 DDC_FIFO_EMPT
Y
788
High-Definition Multimedia Interface (HDMI)
Preliminary
Description
Reserved
Ri and Ri do not match during frame 127 (ICNT .1).
Ri and Ri do not match during frame 0 (ICNT).
Ri did not change between frame 127 and 0.
Ri not read within one frame.
DDC FIFO is half full.
DDC FIFO is full.
DDC FIFO is empty. Reset value is 0, but can be set after reset since the fifo is empty.
© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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