Pm_Ctl_Stat Register; Pm_Ctl-Stat Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

www.ti.com

13.4.11.2 PM_CTL_STAT Register

31
23
CLK_CTRL_EN
R-0
15
PME_STATUS
R/W1C-0
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Bit Field
31-24 DATA_REG
23 CLK_CTRL_EN
22 BW_B3_SUPPORT
21-16 Reserved
15 PME_STATUS
14-13 DATA_SCALE
12-9 DATA_SELECT
8 PME_EN
7-4 Reserved
3 NO_SOFT_RST
2 Reserved
1-0 PWR_STATE
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Figure 13-136. PM_CTL_STAT Register
DATA_REG
R-0
22
B2_B3_SUPPORT
R-0
14 13
DATA_SCALE
R-0
4
NO_SOFT_RST
R-0
Table 13-146. PM_CTL-STAT Register Field Descriptions
Value Description
0-FFh Data register for additional information. Not supported.
0 Bus Power/Clock Control Enable. Hardwired to zero.
0 B2 and B3 support. Hardwired to zero.
0 Reserved
0 PME Status. Indicates if a previously enabled PME event occurred or not.
0-3h Data Scale. Not supported.
0-Fh Data select. Not supported.
0 PME Enable. Value of 1 indicates device is enabled to generate PME. Writable from internal
bus interface.
0 Reserved
0 No soft reset. It is set to disable reset during a transition from D3 to D0. Writable from
internal bus interface.
0 Reserved
0-3h Power State. Controls the device power state. Writes are ignored if the state is not
supported. Writable from internal bus interface.
0 D0 power state
1h D1 power state
2h D2 power state
3h D3 power state
© 2011, Texas Instruments Incorporated
21
Reserved
12
DATA_SELECT
R-0
3 2
Reserved
R-0
Peripheral Component Interconnect Express (PCIe)
Registers
24
16
R-0
9 8
PME_EN
R/W-0
1 0
PWR_STATE
R/W-0
1385