Baud Rate Generator - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
19.2.10 Programmable Baud Rate Generator
The UART/rRDA/CIR module contains a programmable baud generator and a set of fixed dividers that
takes the 48 MHz clock input and divides it down to the expected baud-rate. The baud rate generator
and associated controls is shown in
It is mandatory that the MODESELECT bit in MDR1[2:0] = 7h (disable)
before initializing or modifying clock parameter controls (DLH and DLL).
Failure to observe this rule can result in unpredictable module behavior.
Choosing the appropriate divisor value:
• UART 16× mode: Divisor value = Operating Frequency/(16× baud rate)
• UART 13× mode: Divisor value = Operating Frequency/(13× baud rate)
• SIR mode: Divisor value = Operating Frequency/(16× baud-rate)
• MIR mode: Divisor value = Operating Frequency/(41×/42× baud-rate)
• FIR mode: Divisor value = none
14 bits divisor:
1/(DLH,DLL)
DLH
1710
UART/IrDA/CIR Module
Preliminary
Figure 19-27.
CAUTION
Figure 19-27. BAUD Rate Generator
16x divisor (SIR)
41x,42x (MIR)
MDR1[2:0]:
DLL
MODESELECT
6x divisor
77x divisor (1.6 m s ON)
341x divisor (7.1 m s OFF)
© 2011, Texas Instruments Incorporated
RX SIR (16x)
RX MIR (41x, 42x)
TX SIR/MIR
SIR/MIR
FIR
TX FIR
RX FIR (6x)
1.6/7.1 m s SIP (MIR or FIR)
or
1.6 m s pulse (SIR)
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uart-033
SPRUGX9 – 15 April 2011