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10.3.5 Pin Data Input Register (PDIN)
The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the
actual value of the pin to be read, regardless of the state of PFUNC and PDIR. The value after reset for
registers 1 through 15 and 24 through 31 depends on how the pins are being driven. The PDIN is
shown in
Figure 10-42
Writing to Reserved Bits
Writing a value other than 0 to reserved bits in this register may cause
improper device operation.
31
30
AFSR
AHCLKR
R/W-0
R/W-0
23
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUGX9 – 15 April 2011
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Preliminary
and described in
Table
10-14.
CAUTION
Figure 10-42. Pin Data Input Register (PDIN)
29
28
ACLKR
AFSX
R/W-0
R/W-0
Reserved
R-0
5
4
AXR5
AXR4
R/W-0
R/W-0
© 2011, Texas Instruments Incorporated
27
26
AHCLKX
ACLKX
R/W-0
R/W-0
3
2
AXR3
AXR2
R/W-0
R/W-0
Multichannel Audio Serial Port (McASP)
Registers
25
24
AMUTE
Reserved
R/W-0
R-0
8
1
0
AXR1
AXR0
R/W-0
R/W-0
1077
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