2-Bit Data Delay Used To Skip A Framing Bit; Example: Use Of Rjust Bit Field With 12-Bit Data Value Abch; Example: Use Of Rjust Bit Field With 20-Bit Data Value Abcde - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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For reception, this problem is solved because receive data is sampled on the first falling edge of CLKR
where an active–high internal FSR is detected. However, data transmission must begin on the rising
edge of the internal CLKX clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus on McBSP.DX. The transmitter then asynchronously detects
the frame–synchronization signal (FSX) going active high and immediately starts driving the first bit to
be transmitted on the McBSP.DX pin.
2-bit delay:
A data delay of two bit periods allows the serial port to interface to different types of T1 framing devices
where the data stream is preceded by a framing bit. During reception of such a stream with data delay
of two bits (framing bit appears after a 1–bit delay and data appears after a 2–bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in
data transferred is an 8–bit value with bits labeled B7, B6, B5, and so on.
CLKR
FSR
DR
11.2.8.5.13 Set the Receive Sign-Extension and Justification Mode
The RJUST bit field (SPCR1_REG[14:13]) determines whether data received by the McBSP is
sign–extended or not and how it is justified.
RJUST bit field selects whether data in RB is right– or left–justified (with respect to the MSB) in
DRR_REG register and whether unused bits in DRR_REG are filled with zeroes or with sign bits.
The following tables show the effects of various RJUST values.
example 12–bit receive–data value ABCh,
receive–data value ABCDEh.
Table 11-11. Example: Use of RJUST Bit Field with 12-Bit Data Value ABCh
RJUST
00b
01b
10b
11b
Table 11-12. Example: Use of RJUST Bit Field with 20-Bit Data Value ABCDE
RJUST
00b
01b
10b
11b
SPRUGX9 – 15 April 2011
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Preliminary
Figure 11-27. 2-Bit Data Delay Used to Skip a Framing Bit
2 Bit Periods
Framing Bit
Table 11-12
Justification
Right
Right
Left
Reserved
Justification
Right
Right
Left
Reserved
© 2011, Texas Instruments Incorporated
Figure 11-27. In this figure, the
B7 B6
Table 11-11 shows the effect on an
shows the effect on an example 20–bit
Extension
Zero fill MSBs
Sign extend data into MSBs
Zero fill LSBs
Reserved
Extension
Zero fill MSBs
Sign extend data into MSBs
Zero fill LSBs
Reserved
Multichannel Buffered Serial Port (McBSP)
Architecture
B5
Value in DRR_REG
0000 0ABCh
FFFF FABCh
ABC0 0000h
Reserved
Value in DRR_REG
000A BCDEh
FFFA BCDEh
ABCD E000h
Reserved
1161