Transmit Clock Generator Block Diagram - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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10.2.2.1 Transmit Clock
The transmit bit clock, ACLKX,
internally generated, as selected by the CLKXM bit. If internally generated (CLKXM = 1), the clock is
divided down by a programmable bit clock divider (CLKXDIV) from the transmit high-frequency master
clock (AHCLKX).
Internally, the McASP always shifts transmit data at the rising edge of the internal transmit clock, XCLK,
(Figure 10-16). The CLKXP mux determines if ACLKX needs to be inverted to become XCLK. If
CLKXP = 0, the CLKXP mux directly passes ACLKX to XCLK. As a result, the McASP shifts transmit
data at the rising edge of ACLKX. If CLKXP = 1, the CLKX mux passes the inverted version of ACLKX
to XCLK. As a result, the McASP shifts transmit data at the falling edge of ACLKX.
The transmit high-frequency master clock, AHCLKX, may be either externally sourced from the
AHCLKX pin or internally generated, as selected by the HCLKXM bit. If internally generated
(HCLKXM = 1), the clock is divided down by a programmable high clock divider (HCLKXDIV) from
McASP internal clock source AUXCLK. The transmit high-frequency master clock may be (but is not
required to be) output on the AHCLKX pin where it is available to other devices in the system.
The transmit clock configuration is controlled by the following registers:
• ACLKXCTL.
• AHCLKXCTL.
ACLKX
pin
AHCLKX
pin
SPRUGX9 – 15 April 2011
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Preliminary
(Figure 10-16) may be either externally sourced from the ACLKX pin or
Figure 10-16. Transmit Clock Generator Block Diagram
0
1
CLKXM
(internal/external)
(ACLKXCTL.5)
0
1
HCLKXM
(AHCLKXCTL.15)
© 2011, Texas Instruments Incorporated
XCLK
(to Figure 17)
0
XCLK
1
CLKXP
(ACLKXCTL.7)
(polarity)
Divider
0
/1... /32
CLKXDIV
1
(ACLKXCTL[4−0])
HCLKXP
(AHCLKXCTL.14)
Divider
/1... /4096
HCLKXDIV
(AHLKXCTL[11−0])
Multichannel Audio Serial Port (McASP)
Architecture
AUXCLK
1025