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Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors

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Preliminary

TMS320C6A816x C6-Integra

DSP+ARM Processors

Technical Reference Manual

Literature Number: SPRUGX9

15 April 2011

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Page 1 Preliminary TMS320C6A816x C6-Integra DSP+ARM Processors Technical Reference Manual Literature Number: SPRUGX9 15 April 2011...
Page 2 Preliminary SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 3: Table Of Contents
......................1.9.1 Overview ....................1.9.2 EDMA Regions ..................1.9.3 Synchronization Events ................1.10 Device Clocking and Flying Adder PLL ......................1.10.1 Overview ....................1.10.2 I/O Domains SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 4 LISA Configuration Locking Register: DMM_LISA_LOCK ........2.4.4 DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3 ......2.4.5 DMM TILER Orientation Registers: DMM_TILER_OR0-DMM_TILER_OR1 ..........2.4.6 DMM PAT Configuration Register: DMM_PAT_CONFIG Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 5 ................. General-Purpose I/O (GPIO) Interface ....................... Introduction ..................4.1.1 Purpose of the Peripheral ......................4.1.2 Features ....................4.1.3 Block Diagram ....................... Architecture ....................4.2.1 Operating Modes SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 6 5.5.1 GPMC_REVISION ................... 5.5.2 GPMC_SYSCONFIG ................... 5.5.3 GPMC_SYSSTATUS ................... 5.5.4 GPMC_IRQSTATUS ................... 5.5.5 GPMC_IRQENABLE ................5.5.6 GPMC_TIMEOUT_CONTROL ..................5.5.7 GPMC_ERR_ADDRESS ..................... 5.5.8 GPMC_ERR_TYPE ....................5.5.9 GPMC_CONFIG Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 7 HDMI_WP Register Descriptions ............6.3.2 HDMI_IP_CORE_SYSTEM Register Descriptions ............6.3.3 HDMI_IP_CORE_GAMUT Register Descriptions ..........6.3.4 HDMI_IP_CORE_AUDIO_VIDEO Register Descriptions ............... 6.3.5 HDMI_IP_CORE_CEC Register Descriptions ................6.3.6 HDMI_PHY Register Descriptions SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 8 7.3.29 I2C Own Address 2 Register (I2C_OA2) ..............7.3.30 I2C Own Address 3 Register (I2C_OA3) ............... 7.3.31 Active Own Address Register (I2C_ACTOA) ............. 7.3.32 I2C Clock Blocking Enable Register (I2C_SBLOCK) Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 9 Power Management ....................9.2.4 Interrupt Requests ...................... 9.2.5 DMA Modes ..................... 9.2.6 Buffer Management ....................9.2.7 Transfer Process ............9.2.8 Transfer or Command Status and Error Reporting SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 10 ................... 10.1.4 Functional Block Diagram 1014 ................10.1.5 Supported Use Case Statement 1017 ..............10.1.6 Industry Standard Compliance Statement 1017 ................... 10.1.7 Definition of Terms 1021 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 11 1113 ..........10.3.35 Transmitter DMA Event Control Register (XEVTCTL) 1114 ..............10.3.36 Serializer Control Registers (SRCTLn) 1115 ......... 10.3.37 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) 1116 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 12 11.3.27 McBSP Receive Channel Enable Register Partition H (RCERH_REG) 1198 ......11.3.28 McBSP Transmit Channel Enable Register Partition G (XCERG_REG) 1199 ......11.3.29 McBSP Transmit Channel Enable Register Partition H (XCERH_REG) 1199 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 13 13.1.1 Overview 1272 ....................... 13.1.2 Features 1272 ..................13.1.3 Features Not Supported 1273 ................... 13.1.4 Functional Block Diagram 1273 ................13.1.5 Supported Use Case Statement 1275 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 14 14.3.2 AlwaysOn Power Domain Modules Attribute 1406 ..............14.3.3 Default Power Domain Modules Attribute 1408 ..............14.3.4 SGX Power Domain Modules Attribute 1408 ..................... 14.4 Clock Management 1409 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 15 15.3.7 Day of the Week Register (WEEKS_REG) 1548 ............ 15.3.8 Alarm Second Register (ALARM_SECONDS_REG) 1548 ............15.3.9 Alarm Minute Register (ALARM_MINUTES_REG) 1549 ............15.3.10 Alarm Hour Register (ALARM_HOURS_REG) 1549 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 16 16.4.6 Command Completion Coalescing Control Register (CCC_CTL) 1598 ........16.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) 1599 ..............16.4.8 BIST Active FIS Register (BISTAFR) 1600 ................16.4.9 BIST Control Register (BISTCR) 1601 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 17 17.3.10 Timer Counter Register (TCRR) 1654 ................17.3.11 Timer Load Register (TLDR) 1654 ................17.3.12 Timer Trigger Register (TTGR) 1655 ............17.3.13 Timer Write Posted Status Register (TWPS) 1655 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 18 1680 ..................19.1.3 UART/Modem Functions 1681 ....................19.1.4 IrDA Functions 1681 ....................19.1.5 CIR Features 1681 ......................19.2 Architecture 1682 ................... 19.2.1 UART Signal Descriptions 1682 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 19 19.3.40 XOFF1 Register 1746 ..................... 19.3.41 XOFF2 Register 1746 ............19.3.42 Transmit Frame Length Low Register (TXFLL) 1747 ............19.3.43 Transmit Frame Length High Register (TXFLH) 1747 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 20 ....................20.7.1 CPU Interrupts 1821 ..................20.7.2 Interrupt Description 1825 .................. 20.7.3 Interrupt Condition Control 1826 ....................20.8 Supported Use Cases 1826 ......................... 20.9 Registers 1827 Contents SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 21 21.9.2 Table of Contents 2028 ....................... 21.10 Image Execution 2030 ..................... 21.10.1 Overview 2030 ..................... 21.10.2 Execution 2030 ................... 21.11 Services for HLOS Support 2031 ........................21.12 Tracing 2031 SPRUGX9 – 15 April 2011 Contents Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 22 ......................1-43. MMU_FAULT_PC ..................1-44. Graphics Accelerator Highlight .................... 1-45. SGX Subsystem Integration ..................... 1-46. SGX Block Diagram ................1-47. OCP Revision Register (OCP_REVISION) List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 23 1-92. Revision Register (SPINLOCK_REV) ............1-93. System Configuration Register (SPINLOCK_SYS_CFG) ..............1-94. System Status Register (SPINLOCK_SYSSTAT) ................1-95. Lock Register (SPINLOCK_LOCK_REG_i) ......................1-96. ELM Integration SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 24 ............1-143. Video PLL Frequency 2 Register (VIDEOPLL_FREQ2) ..............1-144. Video PLL Divider 2 Register (VIDEOPLL_DIV2) ............1-145. Video PLL Frequency 3 Register (VIDEOPLL_FREQ3) List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 25 1-191. USB Clock Control Register (USB_CLK_CTL) ............. 1-192. PLL Observe Clock Control Register (PLL_OBSCLK_CTRL) ..................1-193. DDR RCD Register (DDR_RCD) ................... 1-194. Interrupt Controller in Device SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 26 2-47. Buffer Arrangement for HD Luma Buffers in 128MB 8-bit Mode Container ........2-48. Buffer Arrangement for HD Chroma Buffers in 128MB 16-bit Mode Container ....................2-49. PAT Descriptor Node List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 27 3-19. EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) .... 3-20. EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) ........3-21. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 28 3-67. Transmit Pause Timer Register (TXPAUSE) ..............3-68. MAC Address Low Bytes Register (MACADDRLO) ..............3-69. MAC Address High Bytes Register (MACADDRHI) ..................3-70. MAC Index Register (MACINDEX) List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 29 GPMC Block Diagram ..............5-2. GPMC to 16-Bit Address/Data-Multiplexed Memory ................5-3. GPMC to 16-Bit Nonmultiplexed Memory ..................5-4. GPMC to 8-Bit NAND Device SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 30 5-49. Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ........5-50. Asynchronous Single Write Access (Timing Parameters in Clock Cycles) ....................... 5-51. GPMC_REVISION List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 31 6-11. Clock Management Configuration Register (HDMI_WP_SYSCONFIG) ..........6-12. Raw Interrupt Status Register (HDMI_WP_IRQSTATUS_RAW) ..............6-13. Interrupt Status Register (HDMI_WP_IRQSTATUS) ............6-14. Interrupt Enable Register (HDMI_WP_IRQENABLE_SET) SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 32 ..............6-61. Video Hbit to HSYNC Register (HBIT_2HSYNC2) ............6-62. Video Field2 HSYNC Offset Register (FLD2_HS_OFSTL) ............6-63. Video Field2 HSYNC Offset Register (FLD2_HS_OFSTH) List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 33 6-109. Interrupt Unmask Register (INT_UNMASK4) ................6-110. Interrupt Control Register (INT_CTRL) ............. 6-111. xvYCC_2_RGB Control Register (XVYCC2RGB_CTL) ..........6-112. xvYCC_2_RGB Conversion Y_2_R Register (Y2R_COEFF_LOW) SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 34 Synchronization of Two I2C Clock Generators ................. 7-9. Receive FIFO Interrupt Request Generation ................ 7-10. Transmit FIFO Interrupt Request Generation ................7-11. Receive FIFO DMA Request Generation List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 35 .................... 8-9. INTCPS_SIR_IRQ Register ..................... 8-10. INTCPS_SIR_FIQ Register ..................8-11. INTCPS_CONTROL Register ..................8-12. INTCPS_PROTECTION Register ....................8-13. INTCPS_IDLE Register ..................8-14. INTCPS_IRQ_PRIORITY Register SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 36 ................9-35. System Test Register (SD_SYSTEST) ..................9-36. Configuration Register (SD_CON) ................9-37. Power Counter Register (SD_PWCNT) ................ 9-38. Card Status Response Error (SD_SDMASA) List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 37 10-25. Processor Service Time Upon Transmit DMA Event (AXEVT) 1041 ........... 10-26. Processor Service Time Upon Receive DMA Event (AREVT) 1042 ............... 10-27. McASP Audio FIFO (AFIFO) Block Diagram 1044 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 38 10-74. DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) 1116 ........... 10-75. DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) 1116 ..........10-76. DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) 1116 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 39 ....................11-37. McBSP_RCR2_REG 1181 ....................11-38. McBSP_RCR1_REG 1182 ....................11-39. McBSP_XCR2_REG 1183 ....................11-40. McBSP_XCR1_REG 1184 ....................11-41. McBSP_SRGR2_REG 1185 ....................11-42. McBSP_SRGR1_REG 1186 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 40 12-11. Chip-Select SPIEN Timing Controls 1229 ............... 12-12. Transmit/Receive Mode With No FIFO Used 1233 ............12-13. Transmit/Receive Mode With Only Receive FIFO Enabled 1233 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 41 13-22. OB_SIZE Register 1314 ....................13-23. DIAG_CTRL Register 1315 ....................... 13-24. ENDIAN Register 1315 ....................13-25. PRIORITY Register 1316 ...................... 13-26. IRQ_EOI Register 1316 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 42 13-71. PCS_STATUS Register 1340 ..................... 13-72. SERDES_CFG0 Register 1341 ..................... 13-73. SERDES_CFG1 Register 1342 ..................13-74. VENDOR_DEVICE_ID Register 1343 ..................13-75. STATUS_COMMAND Register 1344 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 43 13-120. PCIE_UNCERR_SVRTY Register 1376 ....................13-121. PCIE_CERR Register 1377 ..................13-122. PCIE_CERR_MASK Register 1378 ....................13-123. PCIE_ACCR Register 1379 ....................13-124. HDR_LOG0 Register 1379 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 44 14-21. CM_SYSCLK5_CLKSEL Register 1433 ................... 14-22. CM_SYSCLK6_CLKSEL Register 1433 ................... 14-23. CM_SYSCLK7_CLKSEL Register 1434 .................. 14-24. CM_SYSCLK10_CLKSEL Register 1434 .................. 14-25. CM_SYSCLK11_CLKSEL Register 1435 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 45 14-70. PM_ACTIVE_PWRSTST Register 1469 ..................14-71. RM_ACTIVE_RSTCTRL Register 1470 ..................14-72. RM_ACTIVE_RSTST Register 1470 ................14-73. PM_DEFAULT_PWRSTCTRL Register 1471 ................. 14-74. PM_DEFAULT_PWRSTST Register 1472 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 46 14-119. CM_ALWON_OCMC_0_CLKCTRL Register 1516 ..............14-120. CM_ALWON_OCMC_1_CLKCTRL Register 1517 ..............14-121. CM_ALWON_CONTRL_CLKCTRL Register 1518 ................. 14-122. CM_ALWON_GPMC_CLKCTRL Register 1519 ............... 14-123. CM_ALWON_ETHERNET_0_CLKCTRL Register 1520 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 47 16-3. Global HBA Control Register (GHC) 1595 ..................16-4. Interrupt Status Register (IS) 1596 ..................16-5. Ports Implemented Register (PI) 1597 ..................16-6. AHCI Version Register (VS) 1597 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 48 17-14. Timer IRQ Wakeup Enable Register (IRQWAKEEN) 1652 ..................17-15. Timer Control Register (TCLR) 1652 ..................17-16. Timer Counter Register (TCRR) 1654 ..................17-17. Timer Load Register (TLDR) 1654 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 49 19-22. Transmit FIFO DMA Request Generation (56 Spaces) 1703 ............. 19-23. Transmit FIFO DMA Request Generation (8 Spaces) 1704 .............. 19-24. Transmit FIFO DMA Request Generation (1 Space) 1704 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 50 19-71. Received Frame Length Low Register (RXFLL) 1748 ..............19-72. Received Frame Length High Register (RXFLH) 1748 ............... 19-73. UART Autobauding Status Register (UASR) 1749 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 51 20-46. USBSS IRQ_DMA_ENABLE_1 Register (IRQDMAENABLE1) 1846 ....... 20-47. USBSS IRQ_FRAME_THRESHOLD_TX0_0 Register (IRQFRAMETHOLD00) 1847 ....... 20-48. USBSS IRQ_FRAME_THRESHOLD_TX0_1 Register (IRQFRAMETHOLD01) 1847 ....... 20-49. USBSS IRQ_FRAME_THRESHOLD_TX0_2 Register (IRQFRAMETHOLD02) 1848 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 52 20-95. USB1 IRQ_STATUS_1 Register (USB0IRQSTAT1) 1897 ..........20-96. USB1 IRQ_ENABLE_SET_0 Register (USB1IRQENABLESET0) 1899 ..........20-97. USB1 IRQ_ENABLE_SET_1 Register (USB1IRQENABLESET1) 1901 ..........20-98. USB1 IRQ_ENABLE_CLR_0 Register (USB1IRQENABLECLR0) 1903 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 53 20-145. Function Address Register (USBn_FADDR) 1943 ..............20-146. Power Management Register (USBn_POWER) 1943 ......20-147. Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 15 (USBn_INTRTX) 1944 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 54 21-4. Public RAM Memory Map 1992 ..................21-5. ROM Code Start-up Sequence 1994 ..................21-6. . ROM Code Booting Procedure 1996 ...................... 21-7. Fast External Boot 1999 List of Figures SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 55 2019 ..................21-22. Peripheral Booting Procedure 2021 .................. 21-23. PCIe Peripheral Booting Procedure 2023 ......................21-24. Image Formats 2027 ......................21-25. TOC Structure 2028 SPRUGX9 – 15 April 2011 List of Figures Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 56 1-45. Hardware Implementation Information Register (OCP_HWINFO) Field Descriptions ......... 1-46. System Configuration Register (OCP_SYSCONFIG) Field Descriptions ........1-47. Raw IRQ 0 Status Register (OCP_IRQSTATUS_RAW_0) Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 57 1-93. Global Initialization of Surrounding Modules for System Mailbox ..................... 1-94. Mailbox Global Initialization ................. 1-95. Sending a Message (Polling Method) ................1-96. Sending a Message (Interrupt Method) SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 58 ..........1-142. ELM_SYNDROME_FRAGMENT_0_i Register Field Descriptions ..........1-143. ELM_SYNDROME_FRAGMENT_1_i Register Field Descriptions ..........1-144. ELM_SYNDROME_FRAGMENT_2_i Register Field Descriptions ..........1-145. ELM_SYNDROME_FRAGMENT_3_i Register Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 59 1-192. Audio PLL Divider 3 Register (AUDIOPLL_DIV3) Field Descriptions ........1-193. Audio PLL Frequency 4 Register (AUDIOPLL_FREQ4) Field Descriptions ..........1-194. Audio PLL Divider 4 Register (AUDIOPLL_DIV4) Field Descriptions SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 60 Case 1 Memory Controllers ....................2-5. Controller Configuration .................... 2-6. Case 2 Memory Controllers ....................2-7. Controller Configuration ....................2-8. Section Mapping Option 1 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 61 3-23. EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) Field Descriptions 3-24. EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) Field Descriptions SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 62 3-71. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ....3-72. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 63 GPMC Clocks ..................5-7. GPMC_CONFIG1_i Configuration ................5-8. GPMC Local Power Management Features ....................5-9. GPMC Interrupt Events ..................5-10. Idle Cycle Insertion Configuration SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 64 ......................5-55. GPMC Registers ................. 5-56. GPMC_REVISION Field Descriptions ................5-57. GPMC_SYSCONFIG Field Descriptions ................5-58. GPMC_SYSSTATUS Field Descriptions ................5-59. GPMC_IRQSTATUS Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 65 6-13. PCM, 24-Bit Format ..................6-14. Speaker Mapping Versus Channel ..................... 6-15. IEC 60958 Sample Format ....................... 6-16. IEC 60937 Format ..................6-17. HDMI_WP Registers Summary SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 66 6-64. Video H Resolution Register (HRES_H) Field Descriptions ........... 6-65. Video V Resolution Low Register (VRES_L) Field Descriptions ............6-66. Video V Resolution Register (VRES_H) Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 67 .............. 6-113. Interrupt Source Register (INTR3) Field Descriptions .............. 6-114. Interrupt Source Register (INTR4) Field Descriptions ..........6-115. Interrupt Unmask Register (INT_UNMASK1) Field Descriptions SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 68 6-161. ACR N Software Value Register (N_SVAL2) Field Descriptions ................... 6-162. N_SVAL3 Field Descriptions ..................6-163. CTS_SVAL1 Field Descriptions ..................6-164. CTS_SVAL2 Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 69 6-209. MPEG_VERS Field Descriptions ..................6-210. MPEG_LEN Field Descriptions ..................6-211. MPEG_CHSUM Field Descriptions ............6-212. MPEG_DBYTE__0-MPEG_DBYTE__26 Field Descriptions ............6-213. GEN_DBYTE__0-GEN_DBYTE__30 Field Descriptions SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 70 7-13. Receive DMA Enable Set Register (I2C_DMARXENABLE_SET) Field Descriptions ......7-14. Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET) Field Descriptions ......7-15. Receive DMA Enable Clear Register (I2C_DMARXENABLE_CLR) Field Descriptions List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 71 Response Type Summary ................... 9-3. Local Power Management Features ....................9-4. Clock Activity Settings ........................9-5. Events ............... 9-6. Memory Size, BLEN, and Buffer Relationship SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 72 10-11. Pin Function Register (PFUNC) Field Descriptions 1072 ..............10-12. Pin Direction Register (PDIR) Field Descriptions 1074 ............10-13. Pin Data Output Register (PDOUT) Field Descriptions 1076 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 73 11-12. Example: Use of RJUST Bit Field with 20-Bit Data Value ABCDE 1161 ........11-13. FSRM and GSYNC Effects on Frame-Sync Signal and McBSP.FSR Pin 1162 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 74 ................11-59. McBSP_XCCR_REG Field Descriptions 1208 ................11-60. McBSP_RCCR_REG Field Descriptions 1209 ..............11-61. McBSP_XBUFFSTAT_REG Field Descriptions 1210 ..............11-62. McBSP_XBUFFSTAT_REG Field Descriptions 1210 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 75 13-23. PMCFG Register Field Descriptions 1313 ................. 13-24. ACT_STATUS Register Field Descriptions 1314 ................13-25. OB_SIZE Register Field Descriptions 1314 ................13-26. DIAG_CTRL Register Field Descriptions 1315 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 76 13-72. PCS_CFG0 Register Field Descriptions 1339 ................13-73. PCS_CFG1 Register Field Descriptions 1340 ................. 13-74. PCS_STATUS Register Field Descriptions 1340 ............... 13-75. SERDES_CFG0 Register Field Descriptions 1341 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 77 13-121. DEV_CAP2 Register Field Descriptions 1371 ..............13-122. DEV_STAT_CTRL2 Register Field Descriptions 1371 ................. 13-123. LINK_CTRL2 Register Field Descriptions 1372 ................13-124. PCIe Extended Capability Registers 1373 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 78 14-12. Power Domain Control and Status Registers 1403 ................14-13. Active Power Domain Modules Attribute 1406 ............... 14-14. AlwaysOn Power Domain Modules Attribute 1406 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 79 14-60. CM_TIMER4_CLKSEL Register Field Descriptions 1445 ............... 14-61. CM_TIMER5_CLKSEL Register Field Descriptions 1445 ............... 14-62. CM_TIMER6_CLKSEL Register Field Descriptions 1446 ............14-63. CM_SYSCLK23_CLKSEL Register Field Descriptions 1446 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 80 14-109. CM_ALWON_MCASP0_CLKCTRL Register Field Descriptions 1491 ..........14-110. CM_ALWON_MCASP1_CLKCTRL Register Field Descriptions 1492 ..........14-111. CM_ALWON_MCASP2_CLKCTRL Register Field Descriptions 1493 ..........14-112. CM_ALWON_MCBSP_CLKCTRL Register Field Descriptions 1494 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 81 15-8. Day of the Month (DAYS_REG) Field Descriptions 1546 .............. 15-9. Month Register (MONTHS_REG) Field Descriptions 1547 ..............15-10. Year Register (YEARS_REG) Field Descriptions 1547 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 82 16-28. Port Task File Data Register (P#TFD) Field Descriptions 1617 ..............16-29. Port Signature Register (P#SIG) Field Description 1617 ........... 16-30. Port Serial ATA Status Register (P#SSTS) Field Descriptions 1618 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 83 18-13. WDT_WDSC Register Field Descriptions 1669 ................18-14. WDT_WDST Register Field Descriptions 1670 ................18-15. WDT_WISR Register Field Descriptions 1670 ................18-16. WDT_WIER Register Field Descriptions 1671 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 84 19-36. BOF Control Register (BLR) Field Descriptions 1734 ............19-37. Auxiliary Control Register (ACREG) Field Descriptions 1735 ............19-38. Supplementary Control Register (SCR) Field Descriptions 1736 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 85 20-26. 53 Bytes Test Packet Content 1819 ....................20-27. Subsystem Interrupts 1822 ........... 20-28. CPPI DMA Packet Completion Hardware Interrupt Groupings 1822 ....................20-29. Controller Interrupts 1824 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 86 20-76. USB0 Revision Register (USB0REV) Field Descriptions 1858 ............20-77. USB0 Control Register (USB0CTRL) Field Descriptions 1859 ............20-78. USB0 Status Register (USB0STAT) Field Descriptions 1860 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 87 20-126. Rx Channel N Global Configuration Register (RXGCRn) Field Descriptions 1922 ....20-127. Rx Channel N Host Packet Configuration Register A (RXHPCRAn) Field Descriptions 1923 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 88 20-174. Control Status Register for Endpoint 0 in Peripheral Mode (USBn_PERI_CSR0) Field Descriptions 1953 ..20-175. Control Status Register for Endpoint 0 in Host Mode (USBn_HOST_CSR0) Field Descriptions 1954 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 89 21-9. XIP Timings Parameters 2002 ....................21-10. Pins Used for NOR Boot 2002 ................... 21-11. NAND Timings Parameters 2005 ................. 21-12. ONFI Parameters Page Description 2005 SPRUGX9 – 15 April 2011 List of Tables Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 90 2028 ......................21-35. TOC Item Fields 2029 ...................... 21-36. Filenames in TOC 2029 ..................21-37. Booting Parameters Structure 2030 ......................21-38. Tracing Vectors 2031 List of Tables SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 91: Preface
This TRM has been designated Preliminary because the documentation is in the formative or design phase of development. Texas Instruments reserves the right to change this TRM without notice. Visit the Texas Instruments website at www.ti.com...
Page 92 Read This First SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 93: Chip Level Resources
1.12 Inter-Processor Communication ......................1.13 Mailbox ......................1.14 Spinlock ..................1.15 Error Location Module ....................1.16 Control Module ..................1.17 Interrupt Controller ......................1.18 Resets SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 94: Introduction
Cortex-A8. The high-frequency domain is isolated from the rest of the device by asynchronous bridges. Figure 1-1 shows the high-level block diagram of the MPU subsystem. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 95: 1.2.2 Features
– L1 and L2 Instruction and Data Cache of 32 KB , 4-way, 16 word line with 128 bit interface. – Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 96: 1.2.3 Mpu Subsystem Integration
SYSCLK2 which is fed by the power, reset, and clock management (PRCM) module of the device. In-Circuit Emulator: It is fully Compatible with CoreSight Architecture and enables debugging capabilities. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 97: Microprocessor Unit (Mpu) Subsystem Signal Interface
NEON_RST ARM Cortex-A8 NEON Device modules Interrupts sys_nirq PRCM INTC CORE_RST MOCP AXI2OCP MPU_CLK MOCP clock generator L3_ICLK MPU_RST Non-OCP Level I2Async T2Async shift SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 98: 1.2.4 Mpu Subsystem Clock And Reset Distribution
MPU subsystem INTC_FCLK (ARM_FCLK/2) INTC AXI2OP_FCLK (ARM_FCLK/2) AXI2OCP I2ASYNC_FCLK (ARM_FCLK/2) MPU_CLK clock I2Async generator ICECRUSHER_FCLK (ARM_FCLK/2) PRCM ICECrusher ARM_FCLK ARM Cortex-A8 EMU_CLOCKS Emulation/ DPLL trace/debug Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 99: Mpu Subsystem Clock Frequencies
Resets to the MPU subsystem are provided by the PRCM and controlled by the clock generator module. For details about clocks, resets, and power domains, see the Power, Reset, and Clock Management (PRCM) chapter. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 100: Reset Scheme Of The Mpu Subsystem
ICECrusher Table 1-3. Reset Scheme of the MPU Subsystem Signal Name Interface MPU_RST PRCM NEON_RST PRCM CORE_RST PRCM MPU_RSTPWRON PRCM EMU_RST PRCM EMU_RSTPWRON PRCM Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 101: 1.2.5 Arm Subchip
Closely coupled INTC to the Monza core with 128 interrupt lines Vectored Interrupt Controller Port Present. JTAG based debug Supported via DAP Trace support Supported via TPIU External Coprocessor Not supported SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 102: 1.2.6 Axi2Ocp And I2Async Bridges
AXI slave AXI2OCP_FCLK OCP2.0 (32 bit) To INTC master (INTC) AXI2OCP MPU_RST OCP master (L3) OCP2.0 (64 bit) No OCP I2Async T2Async I2ASYNC_CLK Levelshift Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 103: Read Channel Axi Id To Ocp Tag Mappings
4’b1010 Eviction #3 (including PLE) Thread_Mx 5'b11010 4’b1011 Eviction #4 (including PLE) Thread_Mx 5'b11011 4’b0010 Reserved 4’b0100 4’b0101 4’b0110 4’b0111 4’b1100 4’b1101 4’b1110 4’b1111 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 104: 1.2.7 Interrupt Controller
Table 1-7 shows the different power domains of the MPU subsystem and the modules inside. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 105: Mpu Subsystem Power Domain Overview
For each power domain the PRCM manages all transitions by controlling domain clocks, domain resets, domain logic power switches and memory power switches. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 106: Mpu Power States
Active Disabled or enabled Standby Active Disabled or enabled Standby Standby Active Disabled or enabled Standby Active Disabled or enabled Disabled or enabled 106 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 107: 1.2.9 Host Arm Address Map
1. Reset the INTC (CORE_RST) and the MPU subsystem modules (MPU_RST). The clocks must be active during the MPU reset and CORE reset. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 108 For the complete programming model, see the ARM® Cortex™-A8 Technical Reference Manual. For more information about ARM cortexA8 please refer the website below: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344c/index.html Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 109: C674X Dsp Subsystem
For more information, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5), the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8), and the TMS320C674x DSP Cache User’s Guide (SPRUG82). SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 110: 1.3.2 Key Features
– L1 (program and data): 32-KB 4-way set associative cache-32-byte cache line – L2 (program and data): 128-KB 8-way set associative cache-32-byte cache line Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 111: 1.3.3 Dsp Subsystem Functional Description
The DSP subsystem provides one slave port and one master port, which are connected to the L3 interconnect. Figure 1-8 shows the block diagram of the DSP subsystem. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 112: 1.3.4 Tms320C674X Megamodule
– Interrupt controller (INTC) – Power-down controller (PDC) – Bandwidth manager (BWM) • Advanced event triggering (AET) Figure 1-9 shows a block diagram of the DSP megamodule. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 113: Tms320C674X Megamodule Block Diagram
Fair priority-based arbitration between the DSP, DMA, and cache controller for access to the SRAM • Hardware coherence maintenance with L2 (snooping) • Block global program-initiated cache coherence support (write-back, invalidate, write-back-invalidate) • Freeze and bypass mode SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 114 Figure 1-10 shows a block diagram of the DSP INTC megamodule. For more information on the INTC, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 115: Dsp Megamodule Intc Block Diagram
Unified memory controller (UMC) • Extended memory controller (EMC) • Internal Direct Memory Access controller (IDMA) • L1P memory • L1D memory • L2 memory SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 116: Advanced Event Triggering (Aet)
Counters: count the occurrence of an event or cycles for performance monitoring. • State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 117: System Mmu
L3 interconnect. For MMU interrupt details, refer to the device datasheet. Figure 1-11 shows typical MMU integration. Figure 1-11. Typical MMU Intergration Requestor Resources (memory, peripherals) L3 interconnect SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 118: 1.4.3 Mmu Functional Description
If the requested translation is not in the TLB, the table-walking logic retrieves this translation from the translation table(s), and then updates the TLB. The address translation is then performed. Figure 1-13 summarizes the process. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 119: Mmu Address Translation Process
The translation properties for a big memory section. This memory section can be either 1MB (section) or 16MB (supersection). In this case, all translation parameters are specified in the first-level translation table entry. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 120: Translation Hierarchy
To summarize, the translation table base and the translation table index together define the first-level descriptor address. The precise mechanism used to calculate this address is shown in Figure 1-16. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 121: Detailed First-Level Descriptor Address Calculation
The second-level translation table entries specify the actual translation properties. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 122: Section Translation Summary
Sections and supersections can be translated based solely on the information in the first-level translation table. Figure 1-17. Section Translation Summary Virtual Address 20 19 First-level TranslationTable Section Base Address (From First-level Descriptor) 20 19 Physical Address Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 123: Supersection Translation Summary
16 identical consecutive entries for a supersection. Figure 1-18. Supersection Translation Summary Virtual address 24 23 First-level translation table Supersection base address (From first-level descriptor) 24 23 Physical address SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 124: Two-Level Translation
NOTE: In the case of a large page, the same descriptor must be repeated 16 times. If an access points to a descriptor that is not initialized, the MMU will behave in an unpredictable way." Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 125: Small Page Translation Summary
X = n/a Figure 1-20. Small Page Translation Summary Virtual address 20 19 12 11 First-level translation table First-level descriptor Second-level translation table Physical address SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 126: Large Page Translation Summary
16 identical consecutive entries for a large page. Figure 1-21. Large Page Translation Summary Virtual address 20 19 16 15 First-level translation table First-level descriptor Second-level translation table Physical address Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 127: Tlb-Entry Lock Mechanism
TLB flush. If an entry is set as preserved, it is not deleted when a TLB is flushed, that is, when [0] GLOBALFLUSH is set to 1. Preserved entries must be deleted manually. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 128: Tlb-Entry Structure
Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 129: Mmu Local Power Management Features
TLB is flushed during address translation or a table walk. Permitted; the flush is processed first, followed by the TWL update. MMU is disabled while an interrupt is pending. Not permitted; all pending interrupts should be processed before disabling the MMU. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 130: 1.4.4 Mmu Low-Level Programming Models
MMU_LOCK = 0x- MMU_LOCK = 0x- Disable walking logic Enable walking logic MMU_CNTL[0] TWLENABLE = 0x0 MMU_CNTL[0] TWLENABLE = 0x1 Enable MMU_CNTL [1] MMUENABLE = 0x1 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 131: Mmu_Sysstatus
TLB and do not require retrieval using the table walking process. Table 1-18. Protecting TLB Entries Step Register/Bitfield/Programming Model Value Locks the TLB entries MMU_LOCK[14:10] BASEVALUE SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 132: Mmu_Gflush
Value Set the current victim pointer MMU_LOCK[8:4] CURRENTVICTIM Read RAM parts of the TLB entry MMU_READ_RAM Read CAM parts of the TLB entry MMU_READ_CAM Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 133: 1.4.5 Mmu Registers
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-23. MMU_REVISION Field Descriptions Field Value Description 31-0 REVISION IP Revision. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 134: Mmu_Sysconfig Field Descriptions
Read 0x1: never happens AUTOIDLE Internal interconnect clock gating strategy. Interconnect clock is free-running. Automatic interconnect clock gating strategy is applied, based on the interconnect interface activity. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 135: Mmu_Sysstatus Field Descriptions
Table 1-25. MMU_SYSSTATUS Field Descriptions Field Value Description 31-1 Reserved Reads returns 0. RESETDONE Internal reset monitoring. Internal module reset in on-going. Reset completed. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 136: Mmu_Irqstatus Field Descriptions
Unrecoverable TLB miss (hardware TWL disabled). Read 0x0: TLBMiss false. Write 0x0: TLBMiss status bit unchanged. Write 0x1: TLBMiss status bit is reset. Read 0x1: TLBMiss is true ("pending"). Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 137: Mmu_Irqenable Field Descriptions
TranslationFault event generates an interrupt if occurs. TLBMISS Unrecoverable TLB miss (hardware TWL disabled). TLBMiss interrupt is masked. TLBMiss event generates an interrupt when if occurs. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 138: Mmu_Walking_St
Table Walking Logic enable. TWL disabled. TWL enabled. MMUENABLE MMU enable. MMU disabled. MMU enabled. Reserved Write 0's for future compatibility Reads return 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 139: Mmu_Fault_Ad
Read value : TLB entry that will be updated by table walk logic. Reserved Write 0's for future compatibility Reads return 0. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 140: Mmu_Ld_Tlb Field Descriptions
TLB entry is protected against flush. Valid bit. TLB entry is invalid. TLB entry is valid. PAGESIZE Page size. Section (1MB). Large page (64KB). Small page (4KB). Supersection (16MB). Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 141: Mmu_Ram Field Descriptions
Flush all the non-protected TLB entries when set. Read 0x0: always return 0. Write 0x0: no functional effect. Write 0x1: flush all the non-protected TLB entries. Read 0x1: never happens. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 142: Mmu_Read_Cam
TLB entry is protected against flush. Valid bit. TLB entry is invalid. TLB entry is valid. PAGESIZE Page size. Section (1MB). Large page (64KB). Small page (4KB). Supersection (16MB). Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 143: Mmu_Read_Ram
16-bits 32-bits No translation MIXED Mixed page attribute (use CPU element size). Use TLB element size. Use CPU element size. Reserved Reads return 0. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 144: Mmu_Emu_Fault_Ad
CPU program counter value where cause MMU fault. FFFFh The address value is captured at MMU_EMU_FAULT_AD[31:0] EMUFAULTADDRESS bit field. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to Posted-write. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 145: Sgx530 Graphics Subsystem
SGX530 Graphics Subsystem www.ti.com SGX530 Graphics Subsystem This chapter describes the 2D/3D graphics accelerator (SGX) for the device. NOTE: The SGX subsystem is a Texas Instruments instantiation of the POWERVR SGX530 core ® from Imagination Technologies Ltd. This document contains materials that are ©2003-2007 Imagination Technologies Ltd.
Page 146 – Bilinear, trilinear, anisotropic – Independent minimum and maximum control • Antialiasing: – 4x multisampling – Up to 16x full scene anti-aliasing – Programmable sample positions Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 147 External data access: – Permits reads from main memory using cache – Permits writes to main memory – Data fence facility – Dependent texture reads SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 148: 1.5.2 Sgx Integration
SGX_ICLK interface clock manages the data transfer on the L3 master and slave ports. • SGX_FCLK is the functional clock and is used inside the SGX subsystem to generate SGX 2D and 3D domain clock signals. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 149 The SGX handles the automatic clock gating performed on the multiple internal module clock domains. 1.5.2.2 Hardware Requests 1.5.2.2.1 Interrupt Request The SGX subsystem can generate one interrupt (SGX_IRQ) to the MPU subsystem interrupt controller mapped on M_IRQ_37. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 150: 1.5.3 Sgx Functional Description
(USSE) Pixel Data master General-purpose selector coprocessor data master Power Texturing coprocessor Multilevel cache management control register block SOCIF L3 interconnect L3 interconnect sgx-003 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 151 The address order is determined by the frame buffer mode. The pixel coprocessor contains a dithering and packing function. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 152: 1.5.4 Sgx Registers
Section 1.5.4.1.16 FF04h OCP_INTERRUPT_EVENT Interrupt Events Register Section 1.5.4.1.17 FF08h OCP_DEBUG_CONFIG Configuration of Debug Modes Register Section 1.5.4.1.18 FF0Ch OCP_DEBUG_STATUS Debug Status Register Section 1.5.4.1.19 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 153: Ocp Revision Register (Ocp_Revision) Field Descriptions
Memory bus width is 128 bits SYS_BUS_WIDTH System bus width. System bus width is 32 bits. System bus width is 64 bits. System bus width is 128 bits. Reserved. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 154: System Configuration Register (Ocp_Sysconfig) Field Descriptions
Smart Standby mode. Smart Standby mode. IDLE_MODE Clock Idle mode. Force Idle mode. No idle mode. Smart Idle mode. Smart Idle mode. Reserved Reserved. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 155: Raw Irq 0 Status Register (Ocp_Irqstatus_Raw_0) Field Descriptions
Reserved. TARGET_SINTERRUPT_R Interrupt 1- slave port raw event. Read: No event pending. Read: Event pending. Write: No action. Write: Set event (Used for debug). SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 156: Raw Irq 2 Status Register (Ocp_Irqstatus_Raw_2) Field Descriptions
INIT_MINTERRUPT_STAT Interrupt 0 - Master port status event. Read: No event pending. Read: Event pending and interrupt enabled. Write: No action. Write: Clear event. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 157: Interrupt 1 Status Event Register (Ocp_Irqstatus_1) Field Descriptions
Interrupt 1 - slave port status event. TATUS Read: No event pending. Read: Event pending and interrupt enabled. Write: No action. Write: Clear event. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 158: Enable Interrupt 0 Register (Ocp_Irqenable_Set_0) Field Descriptions
Reserved. TARGET_SINTERRUPT_E Enable interrupt 1 - slave port interrupt. NABLE Read: Interrupt is enabled. Read: Interrupt is disabled. Write: No action. Write: Enable interrupt. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 159: Enable Interrupt 2 Register (Ocp_Irqenable_Set_2) Field Descriptions
Reserved Reserved. INIT_MINTERRU Disable interrupt 0 - master port. PT_DISABLE Read: Interrupt is enabled. Read: Interrupt is disabled. Write: No action. Write: Disable interrupt. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 160: Disable Interrupt 1 Register (Ocp_Irqenable_Clr_1) Field Descriptions
Reserved Reserved. THALIA_IRQ_DISABLE Disable interrupt 2 - Thalia (core) interrupt. Read: Interrupt is enabled. Read: Interrupt is disabled. Write: No action. Write: Disable interrupt. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 161: Configure Memory Page Register (Ocp_Page_Config) Field Descriptions
Defines the page size on internal memory interface. Page size is 4 KB. Page size is 2 KB. Page size is 1 KB. Page size is 520 B. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 162: Interrupt Events Register (Ocp_Interrupt_Event)
Memory page had been crossed during a burst. Read: No event pending. Read: Event pending. Write: Clear the event. Write: Set event and interrupt if enabled (debug only). Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 163: Interrupt Events Register (Ocp_Interrupt_Event) Field Descriptions
Receiving response when not expected. Read: No event pending. Read: Event pending. Write: Clear the event. Write: Set event and interrupt if enabled (debug only). SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 164: Configuration Of Debug Modes Register (Ocp_Debug_Config) Field Descriptions
Forces the OCP target port to Idle. Normal mode. No force. Force port to be always Idle. Forces target port to never be in Idle mode. Normal mode. No force. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 165: Debug Status Register (Ocp_Debug_Status) Field Descriptions
Command CHK_WRADDR_PAGE received. Not used. Command CHK_RDADDR_PAGE received. Not used. Command TARGET_REG_WRITE received. Command TARGET_REG_READ received. INIT_MSTANDBY Status of init_MStandby signal. INIT_MWAIT Status of init_MWait signal. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 166 Target MConnect state. Target is in M_OFF state. Target is in M_WAIT disconnect state. Target is in M_DISC state. Target is in M_CON state. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 167: Hd Video Processing Subsystem (Hdvpss)
The NF (Noise Filter) performs a memory to memory spatial/temporal noise filter algorithm on a 422 raster input source and produces a 420 tiled output source. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 168 Supported resolutions are 480i, 480p, 720p, 1080i, 1080p. Note that the maximum supported line width is 1920 pixels. Furthermore, width and height values must always be an even number. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 169 Each video capture port supports one programmable color space conversion to convert 24-bit RGB data to YCbCr data. • The HDVPSS supports data storage in 444, 422, and 420 formats. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 170: System Memory Map
DEI to reduce overall bandwidth. System Memory Map For detailed specification on memory mapping, see the device-specific data manual. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 171: Device Interrupts
HDVPSSINT HD-VPSS HD-VPSS Interrupt GFXINT SGX530 Error in the IMG bus interrupt HDMIINT HDMI HDMI Interrupt Reserved Reserved MACRXTHR0 CPGMAC0 CPGMAC0 Receive threshold interrupt SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 172 MCARXINT1 McASP1 McASP 1 Receive interrupt MCATXINT2 McASP2 McASP 2 Transmit interrupt MCARXINT2 McASP2 McASP 2 Receive interrupt MCBSPINT McBSP McBSP Common(TX/RX) Interrupt 172 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 173 HVT SmartReflex interrupt SYSMMUINT System MMU Table walk abort interrupt MCMMUINT Media Controller MMU Fault interrupt DMMINT PAT Fault interrupt Reserved Reserved Reserved Reserved Reserved Reserved SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 174: 1.8.2 Interrupt Requests To Media Controller Intc
Reserved Reserved Reserved Reserved Reserved I2CINT0 I2C0 I2C0 interrupt I2CINT1 I2C1 I2C1 interrupt UARTINT0 UART0 UART/IrDA 0 interrupt UARTINT1 UART1 UART/IrDA 1 interrupt 174 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 175 GPIO 1 interrupt 2 SDINT SD/SDIO SDIO interrupt SPIINT McSPI SPI Interrupt Reserved Reserved Reserved Reserved SMRFLXINT1 SmartReflex1 HVT SmartReflex interrupt level version Reserved Reserved SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 176: 1.8.3 Interrupt Requests To Dsp Intc
CPGMAC1 Receive threshold interrupt MACRXINT1 CPGMAC1 CPGMAC1 Receive pending interrupt MACTXINT1 CPGMAC1 CPGMAC1 Transmit pending interrupt MACMISC1 CPGMAC1 CPGMAC1 Stat, Host, MDIO LINKINT or MDIO USERINT 176 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 177 McBSP McBSP Common(TX/RX) Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 178 L2 CPU memory protection fault event UMC_DMPA L2 DMA memory protection fault event EMC_CMPA IDMA CPU memory protection fault event EMC_BUSERR IDMA Bus error interrupt event Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 179: Edma And Edma Events
For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, see the Enhanced DMA (EDMA) Controller User's Guide. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 180: Edma Channel Synchronization Events
10 1010 Unused – 10 1011 Unused – 10 1100 Unused – 10 1101 Unused – 10 1110 Unused – 10 1111 Unused – 180 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 181 11 1010 I2CTXEVT0 I2C0 11 1011 I2CRXEVT0 I2C0 11 1100 I2CTXEVT1 I2C1 11 1101 I2CRXEVT1 I2C1 11 1110 Unused – 11 1111 Unused – SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 182: 1.10 Device Clocking And Flying Adder Pll
Table 1-68 and System Clock Domains are described in Table 1-69. Figure 1-67 shows detailed clocking architecture on this device. 182 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 183: Device Clock Inputs
EMAC Reference Clock MAINPLL 125 MHz Interface & Functional SATA SYSCLK5 MAINPLL 250 MHz Clock Interface & Functional PCIe SYSCLK5 MAINPLL 250 MHz Clock SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 184 196 MHz SYSCLK22 Functional Clock AUDIOPLL 196 MHz Interface & Functional SGX530 SYSCLK23 MAINPLL 333 MHz Clock Interface & Functional SYSCLK6 MAINPLL 125 MHz Clock Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 185: Detailed Clock Architecture
SerDes PLL MAILBOX SATA SERDES_CLKPIN SPINLOCK SYSCLK23 SGX530 McASP DDRPLL McBSP DDR2/3 SYSCLK11 SYSCLK17 SMART REFLEX VIDEOPLL SYSCLK15 HDVPSS SYSCLK13 SYSCLK18 AUDIOPLL SYSCLK20, SYSCLK21, SYSCLK22 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 186: 1.10.2 I/O Domains
50 MHz TCLKIN HDMI 48 MHz SYSCLK13, SYSCLK15, SYSCLK17 PCIe/SATA 100 MHz SERDES_CLKP, SERDES_CLKN SD/SDIO 48 MHz SYSCLK6 MAINPLL, DDRPLL, 27 MHz CLKIN1 VIDEOPLL, AUDIOPLL Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 187: 1.10.3 Flying Adder Pll
1.10.3.1 PLL Types This device has 4 on-chip PLLs and they are as follows: 1. MAIN PLL 2. DDR PLL 3. VIDEO PLL SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 188: Main Pll Structure
1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/5, 1/6, 1/8, 1/16 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 188 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 189: Main Pll Clocks
Clock SYSCLK6 Interface Clock MAINPLL 125 MHz McASP0(x3), McBSP SYSCLK6 Interface Clock MAINPLL 125 MHz SGX530 SYSCLK23 Interface & Functional MAINPLL 333 MHz Clock SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 190: Example For Main Pll Frequencies
SYSCLK8 gated clock is used for this purpose. Additionally the SYSCLK8 divider (/A) is tied to 1/1 to ensure that the DDR2/3 controller OCP and L3 interconnect probe remain frequency locked. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 191: Ddr Pll Structure
PRCM for dividers. Table 1-74. DDR PLL Dividers Divider Supported Divide Ratio Default Value 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 192: Example For Ddr Pll Frequencies
1593 0.85 1440 SYSCLK10 SYSCLK9 1593 1593 398.25 SYSCLK8 398.25 1593 398.25 External Clock 1593 0.85 1440 SYSCLK10 SYSCLK9 1593 1593 398.25 SYSCLK8 398.25 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 193: Video Pll Structure
1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1,1/2, 1/22 1/22 1/1,1/2, 1/22 1/22 1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 194: Video Pll Clocks
Frequency( Integ Frac Output (MHz) MHz) tiona (MHz) (MHz) FREQ (MHz) (MHz) 1485 1080 SYSCLK17 SYSCLK16 1485 1188 SYSCLK13 74.25 SYSCLK14 1485 1188 SYSCLK14 SYSCLK15 148.5 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 195: Audio Pll Structure
1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 1/1,1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 196: Audio Pll Clocks
Note that the MAILPLL is powered down after the following device-level global resets: • Power-on Reset (POR) • Warm Reset (RESET) • Max Reset Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 197 8. If MAINPLL is locked in step 7, then clear the MAIN_BP bit in MAINPLL_CTRL to 0 to bring MAINPLL out from bypass mode. Where x = 1, 2, 3, 4, 5 Flying Adder Synthesizer. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 198: 1.10.4 Clock Out
Main pll clock5, divider set to 1/1 and clock disabled. Refer CM_CLKOUT_CTRL register in PRCM PRG for more details. Figure 1-73. Clocks video_pll_clk1 ddr_pll_clk1 main_pll_clock5 audio_pll_clk1 GlitchLess SYSCLKOUT_PRE 1/1 1/2 1/4 1/8 1/16 SYSCLK_OUT Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 199: 1.11 Bus Interconnect
(read response with data payload, write response) transactions. All exposed interfaces of this NoC interconnect, both for Targets and Initiators; comply with the OCPIP2.2 reference standard. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 200: L3 Interconnect Block Diagram
SMSET IF I2ASYNC BR19 BR17 BR18 DMM Tiler 0 Port Connection BR29 OCPASYNC OCPASYNC OCPASYNC OCPASYNC « DMM Tiler 1 Port Connection Debug SS Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 201 McASP1 32-bit target port. • McASP2 32-bit target port. • McBSP 32-bit target port. • HDMI 32-bit target port. • USB 32-bit target port. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 202: Device Mconnid Assignment
USB QMGR SATA PCIe Expansion Port Stat Collctr 0 Stat Collctr 1 Stat Collctr 2 Stat Collctr 3 DMM Page Table Connects only to EMIFs Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 203: L3 Master/Slave Connectivity (Table 1 Of 2)
R1 : Selectable path based on 33rd address bit from Control Module register for System MMU accessible targets. Non-MMU Accessible targets (such as C674x DSP SDMA) will always be direct mapped. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 204: L3 Master/Slave Connectivity (Table 2 Of 2)
TPTC0 WR TPTC1 RD TPTC1 WR TPTC2 RD TPTC2 WR TPTC3 RD TPTC3 WR R : Required path. U: Path exists but is untested. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 205: 1.12 Inter-Processor Communication
(Video-M3, VPSS-M3, C674x™). The Notify method is the API for responding to interrupts. SysLink also incorporates full IPC features including MessageQ, RingIO, and FrameQ. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 206: 1.12.3 Overview And Strategy
• SysLink / IPC – A8 to Video M3 – A8 to VPSS M3 – Video M3 to VPSS M3 – C674x™ to VideoM3 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 207: System Ipcs
MBX_A8_VideoM3 MBX1_U2_VPSSM3 MBX_VideoM3_A8 MBX1_U0_A8 MBX_A8_64x MBX_64x_A8 MBX1_U3_VideoM3 MBX_64x_VPSSM3 MBX_VPSSM3_64x MBX_64x_VideoM3 MBX_VideoM3_64x MBX_VPSSM3_VideoM3 Media Controller MBX_VideoM3_VPSSM3 MBX1_U1_64x VPSS M3 Video M3 Shared C674x Memory Interrupt SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 208: 1.12.4 Ipc Component Configuration
This SoC has 64 spinlocks for the system. Table 1-86. Hardware Spinlock Configuration Hardware Spinlocks Name Configuration 0..63 SPINLOCK_0 .. No configurable options SPINLOCK_63 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 209: 1.13 Mailbox
IDLE hardware handshake Mailbox DSP subsystem (x12) MAIL_U1_IRQ Interrupt controller MAIL_U2_IRQ PRCM MAIL_U3_IRQ SYSCLK6 MAILBOX_FCLK VPSS-M3 VPSS-M3 ALW_DOM_RST_N MAILBOX_RST Interrupt controller Interrupt controller VIDEO-M3 Interrupt controller SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 210: 1.13.3 Functional Description
User 1: DSP subsystem (u = 1) • User 0: Cortex-A8 MPU subsystem (u = 0) • User 1: DSP subsystem (u = 1) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 211: Mailbox Block Diagram
The software must ensure that the software reset completes before doing mailbox operations. 1.13.3.3 Power Management Table 1-91 describes power-management features available for the mailbox module. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 212: Local Power Management Features
An event can generate an interrupt request when a logical 1 is written to the corresponding unmask bit in the MAILBOX_IRQENABLE_SET_u register. Events are reported in the appropriate MAILBOX_IRQSTATUS_CLR_u and MAILBOX_IRQSTATUS_RAW_u registers. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 213 0 is returned. The new message interrupt is asserted when at least one message is in the mailbox message FIFO queue. To determine the number of messages in the mailbox message FIFO queue, read the MAILBOX_MSGSTATUS_m register. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 214: 1.13.4 Programming Guide
Interrupt Controllers Cortex-A8 MPU or DSP interrupt controller must be configured to enable the interrupt request generation to the Cortex-A8 MPU or DSP subsystem. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 215: Mailbox Global Initialization
IF : Is FIFO full ? MAILBOX_FIFOSTATUS_m[0].FIFOFULL =1h Enable interrupt event MAILBOX_IRQENABLE_SET_u[1+ m*2] User(processor) can perform anothr task until interrupt occurs ELSE Write message MAILBOX_MESSAGE_m[31:0].MESSAG ----h EVALUEMBM ENDIF SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 216: Receiving A Message (Polling Method)
IF : Number of messages is not equal to MAILBOX_MSGSTATUS_m[2:0].NBOFM !=0h SGMB Read message MAILBOX_MESSAGE_m[31:0].MESSAG ----h EVALUEMBM ELSE Write 1 to acknowledge interrupt MAILBOX_IRQSTATUS_CLR_u[0 + m*2] ENDIF Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 217: 1.13.5 Mailbox Registers
Mailbox IRQ Enable Set Register Section 1.13.5.8 _SET_u (2) 010Ch + (10h * MAILBOX_IRQENABLE Mailbox IRQ Enable Clear Register Section 1.13.5.9 _CLR_u (2) 0140h RESERVED Reserved SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 218: Revision Register (Mailbox_Revision)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-104. System Configuration Register (MAILBOX_SYSCONFIG) Field Descriptions Field Value Description 31-0 REVISION 0-FFFF FFFFh IP Revision Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 219: Message Register (Mailbox_Message_M) Field Descriptions
EMBM mailbox. Reads remove the message from the FIFO queue. FIFOFULLMBM Full flag for Mailbox Mailbox FIFO is not full Mailbox FIFO is full SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 220: Message Status Register (Mailbox_Msgstatus_M)
Table 1-107. Message Status Register (MAILBOX_MSGSTATUS_m) Field Descriptions Field Value Description 31-3 Reserved Reserved. NBOFMSGMBM 0-7h Number of unread messages in Mailbox. Limited to four messages per mailbox. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 221: Irq Raw Status Register (Mailbox_Irqstatus_Raw_U) Field Descriptions
New Message Status bit for User u, Mailbox 10 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 222: Irq Raw Status Register (Mailbox_Irqstatus_Raw_U)
Not Full Status bit for User u, Mailbox 5 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 223 New Message Status bit for User u, Mailbox 1 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 224 New Message Status bit for User u, Mailbox 0 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 225: Irq Clear Status Register (Mailbox_Irqstatus_Clr_U) Field Descriptions
New Message Status bit for User u, Mailbox 10 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 226: Irq Clear Status Register (Mailbox_Irqstatus_Clr_U)
Not Full Status bit for User u, Mailbox 5 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 227 New Message Status bit for User u, Mailbox 1 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 228 New Message Status bit for User u, Mailbox 0 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 229: Irq Enable Set Register (Mailbox_Irqenable_Set_U) Field Descriptions
Not Full Status bit for User u, Mailbox 9 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 230: Irq Enable Set Register (Mailbox_Irqenable_Set_U)
New Message Status bit for User u, Mailbox 5 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 231: Irq_Enable_Set Register
Not Full Status bit for User u, Mailbox 0 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 232 New Message Status bit for User u, Mailbox 0 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 233: Irq Enable Clear Register (Mailbox_Irqenable_Clr_U) Field Descriptions
Not Full Status bit for User u, Mailbox 9 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 234: Irq Enable Clear Register (Mailbox_Irqenable_Clr_U)
New Message Status bit for User u, Mailbox 5 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 235 Not Full Status bit for User u, Mailbox 0 Read: No event pending (message queue full) Read: Event pending (message queue not full) Write: No action Write: Set the event (for debug) SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 236 New Message Status bit for User u, Mailbox 0 Read: No event (message) pending Read: Event (message) pending Write: No action Write: Set the event (for debug) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 237: 1.14 Spinlock
Figure 1-88. Spinlock Module Device Spinlock L4_CFG interconnect Lock register 1 Lock register 2 SPINLOCK_ICLK PRCM SPINLOCK_RST Lock register 64 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 238: 1.14.2 Integration
ALW_DOM_R reset is asynchronously SPINLOCK SPINLOCK_RST PRCM ST_N applied to the Spinlock registers. The Spinlock module does not support any interrupt and DMA requests. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 239: 1.14.3 Functional Description
The Spinlock module can now be powered off by writing the appropriate status to the PRCM. In the case of powering off the whole system, these steps are unnecessary. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 240: Spinlock_Lock_Reg_I Register State Diagram
Only 32-bit reads and writes are supported. Figure 1-90. SPINLOCK_LOCK_REG_i Register State Diagram reset read ->0 write 1 Not taken Taken state state read ->1 write 0 write 0/1 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 241: Programming Guide
If the acquisition attempt fails, the acquisition should be re-attempted. To prevent unknown interrupt disabled time, interrupts should be re-enabled and then disabled before re-attempting to acquire the lock. Figure 1-91 shows the described above procedure. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 242: Take And Release Spinlock
Is the lock taken? SPINLOCK_LOCK_REG_i[0] TAKEN = 0 Enable all interrupts Critical code section Free a lock SPINLOCK_LOCK_REG_i[0] TAKEN = 0 Enable all interrupts Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 243: Spinlock Registers
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-118. Revision Register (SPINLOCK_REV) Field Descriptions Field Value Description 31-0 IP Revision Code. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 244: System Configuration Register (Spinlock_Sys_Cfg) Field Descriptions
Interface clock is not gated when the L4-STANDARD interface is idle. Automatic internal interface clock gating strategy is applied, based on the L4-CFG interface activity. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 245: System Status Register (Spinlock_Sysstat) Field Descriptions
At least one of the lock registers 32–63 is in the Taken state. Reserved Reserved RESETDONE Reset done status. Reset in progress. Reset is completed. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 246: Lock Register (Spinlock_Lock_Reg_I)
Set the lock to Not Taken (free). Lock was previously Taken. The requester is not granted the lock and must retry. No update to the lock value. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 247: Error Location Module
Interrupt generation on error-location process completion: – When the full page has been processed in page mode – For each syndrome polynomial in continuous mode SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 248: Elm Integration
Cortex-A8 MPU PRCM subsystem ELM_IRQ SYSCLK6 ELM_FCLK ALW_DOM_RST_N ELM_RST MA_IRQ_4 elm-001 Table 1-122. Integration Attributes Attributes Module Instance Power Domain Wake-Up Capability Interconnect PD_ALWAYS_ON 248 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 249: Elm Functional Description
The PRCM module has no hardware means of reading CLOCKACTIVITY settings. Thus, software must ensure consistent programming between the ELM CLOCKACTIVITY and ELM clock PRCM control bits. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 250: Events
ELM_ERROR_LOCATION_15_i registers are not reset (i = 0 to 7). The software must not consider them until the corresponding ELM_IRQSTATUS[i] LOC_VALID_i bit is set. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 251: Elm_Location_Status_I Value Decoding Table
1. Other status bits must be written to 0 so that other interrupts are not unintentionally cleared. When using this mode, the ELM_IRQSTATUS[8] PAGE_VALID interrupt is never triggered. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 252: Elm Basic Programming Model
The engine goes through the entire error-location process and results can be read. Table 1-129 Table 1-130 describe the processing completion for continuous and page modes, respectively. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 253: Elm Processing Completion For Continuous Mode
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i[12:0] polynomial i of the ECC_NB_ERRORS first ECC_ERROR_LOCATION registers. ELM_ERROR_LOCATION_1_i[12:0] ECC_ERROR_LOCATION ELM_ERROR_LOCATION_15_i[12:0] ECC_ERROR_LOCATION endif End Repeat Clear the ELM_IRQSTATUS register. ELM_IRQSTATUS 0x1FF SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 254: Use Case: Continuous Mode
7 to bit 0, then from bit 15 to bit 8. Based on this convention, an address table of the data buffer can be built. NAND memory addresses in Table 1-132 are given in decimal format. 254 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 255: Use Case
Sets the ELM in page mode (4 blocks in a page) ELM_PAGE_CTRL[0] SECTOR_0 ELM_PAGE_CTRL[1] SECTOR_1 ELM_PAGE_CTRL[2] SECTOR_2 ELM_PAGE_CTRL[3] SECTOR_3 Disable all interrupts for syndrome polynomial and ELM_IRQENABLE 0x100 enable PAGE_MASK interrupt. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 256 (i=1) All errors were successfully located. Read the process exit status for syndrome ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE polynomial 2: (i=2) All errors were successfully located. 256 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 257 0x1036 Read the errors location bit addresses for ELM_ERROR_LOCATION_0_i (i=1) 0x3E8 syndrome polynomial 2 of the first registers: Clear the ELM_IRQSTATUS register. ELM_IRQSTATUS 0x1FF SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 258: Elm Registers
418h + (40h × i) Section 1.15.5.14 Register 800h + (100h × i) ELM_LOCATION_STATUS_i ELM_LOCATION_STATUS_i Register Section 1.15.5.15 880h-8BCh + (100h × ELM_ERROR_LOCATION_0-15_i ELM_ERROR_LOCATION_0-15_i Registers Section 1.15.5.16 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 259: Elm Revision Register (Elm_Revision)
Internal OCP clock gating strategy. (No module visible impact other than saving power.) OCP clock is free-running. Automatic internal OCP clock gating strategy is applied based on the OCP interface activity. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 260: Elm System Status Register (Elm_Sysstatus)
From hardware perspective, the reset state is 0. From software user perspective, when the accessible module is 1. Reset is on-going Reset is done (completed) Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 261: Elm Interrupt Status Register (Elm_Irqstatus)
Error-location status for syndrome polynomial 3. Read: No syndrome processed or process in progress. Read: Error-location process completed. Write: No effect. Write: Clear interrupt. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 262 Error-location status for syndrome polynomial 0. Read: No syndrome processed or process in progress. Read: Error-location process completed. Write: No effect. Write: Clear interrupt. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 263: Elm Interrupt Enable Register (Elm_Irqenable)
Error-location interrupt mask bit for syndrome polynomial 1. Disable interrupt. Enable interrupt. LOCATION_MASK_0 Error-location interrupt mask bit for syndrome polynomial 0. Disable interrupt. Enable interrupt. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 264: Elm Location Configuration Register (Elm_Location_Config)
Maximum size of the buffers for which the error-location engine is used, in number of nibbles (4-bits entities) 15-2 Reserved Reserved ECC_BCH_LEVEL Error correction level. 4 bits. 8 bits. 16 bits. Reserved. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 265: Elm Page Definition Register (Elm_Page_Ctrl)
Set to 1 if syndrome polynomial 1 is part of the page in page mode. Must be 0 in continuous mode. SECTOR_0 Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 266: Elm_Syndrome_Fragment_0_I Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-144. ELM_SYNDROME_FRAGMENT_2_i Register Field Descriptions Field Value Description 31-0 SYNDROME_2 0-FFFF FFFFh Syndrome bits 64 to 95. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 267: 1.15.5.11 Elm_Syndrome_Fragment_3_I Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-147. ELM_SYNDROME_FRAGMENT_5_i Register Field Descriptions Field Value Description 31-0 SYNDROME_5 0-FFFF FFFFh Syndrome bits 160 to 191. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 268: 1.15.5.14 Elm_Syndrome_Fragment_6_I Register
ECC error-location process failed. Number of errors and error locations are invalid. All errors were successfully located. Number of errors and error locations are valid. Reserved Reserved ECC_NB_ERRO 0-1Fh Number of errors detected and located. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 269: 1.15.5.16 Elm_Error_Location_0-15_I Registers
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-150. ELM_ERROR_LOCATION_0-15_i Registers Field Descriptions Field Value Description 31-13 Reserved Reserved 12-0 ECC_ERROR_L 0-1FFFh Error-location bit address. OCATION SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 270: Control Module
CONTROL_STATUS Control Status Register Section 1.16.1.1.1 BOOTSTAT Boot Status Register Section 1.16.1.1.2 DSPBOOTADDR DSP Boot Address Vector Section 1.16.1.1.3 4Ch - 7Ch Reserved Reserved Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 271: Control Status Register (Control_Status)
GPMC CS0 Default Bus Width, from CS0BW pin. 8-bit data bus. 16-bit data bus. 15-5 Reserved Reserved SYSBOOT System Boot Type, from BTMODE pins. These pins determine the primary bootmode. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 272: Boot Status Register (Bootstat)
The Host ARM can poll this bit to determine whether to continue the boot process Host has not complete boot sequence. Host boot sequence is complete. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 273: Dsp Boot Address Register (Dspbootaddr)
Table 1-154. 5.1.3. DSP Boot Address Register (DSPBOOTADDR) Field Descriptions Field Value Description 31-10 BOOTADDR DSP Boot Address (upper 22 bits) FFFFh Reserved Reserved. RSTDONE DSP Reset Done. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 274: Pll Control Registers
Audio PLL Divider 4 Register Section 1.16.1.2.39 4C8h AUDIOPLL_FREQ5 Audio PLL Frequency 5 Register Section 1.16.1.2.40 4CCh AUDIOPLL_DIV5 Audio PLL 5 Divider Register Section 1.16.1.2.41 274 Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 275: Main Pll Control Register (Mainpll_Ctrl)
Reserved. Read returns 0. MAIN_LOC_CTL Select the source to detect PLL lock. Default value of '0' is recommended to use the more reliable Analog circuit. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 276: Main Pll Powerdown Register (Mainpll_Pwd)
Main PLL Clock2 Powerdown. Setting this bit powers down clock 2 (SYSCLK2). PWD_CLK1 Main PLL Clock1 Powerdown. Setting this bit powers down clock 1 (SYSCLK1). Reserved Reserved. Read returns 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 277: Main Pll Frequency 1 Register (Mainpll_Freq1)
Load Synth1 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into Main Synthesizer1. MAIN_MDIV1 0-FFh Synth1 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 278: Main Pll Frequency 2 Register (Mainpll_Freq2)
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into Main Synthesizer2. MAIN_MDIV2 0-FFh Synth2 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 279: Main Pll Frequency 4 Register (Mainpll_Freq4)
Load Synth4 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into Main Synthesizer4. MAIN_MDIV4 0-FFh Synth4 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 280: Main Pll Frequency 5 Register (Mainpll_Freq5)
Load Synth5 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into Main Synthesizer5. MAIN_MDIV5 0-FFh Synth5 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 281: Main Pll Divider 6 Register (Mainpll_Div6)
MAIN_LDMDIV7 Load M Divider7 value. Setting this bit to 1 causes the M Divider7 value to be loaded. MAIN_MDIV7 0-FFh Frequency M Post Divider7. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 282: Ddr Pll Control Register (Ddrpll_Ctrl)
DDR PLL bypass enable. Normal operation. PLL in bypass mode, reference clock driven at output. Reserved Reserved. Read returns 0. DDR_LOC_CTL DDR PLL lock output select. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 283: Ddr Pll Powerdown Register (Ddrpll_Pwd)
Load Synth1 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into DDR Synthesizer1. DDR_MDIV1 0-FFh Synth1 Frequency M Post Divider SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 284: Ddr Pll Frequency 2 Register (Ddrpll_Freq2)
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into DDR Synthesizer2. DDR_MDIV2 0-FFh Synth2 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 285: Ddr Pll Frequency 3 Register (Ddrpll_Freq3)
Load Synth3 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into DDR Synthesizer3. Bit is cleared by hardware after load is complete DDR_MDIV3 0-FFh Synth3 Frequency M Post Divider SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 286: Ddr Pll Frequency 4 Register (Ddrpll_Freq4)
Load Synth4 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into DDR Synthesizer4. DDR_MDIV4 0-FFh Synth4 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 287: Ddr Pll Frequency 5 Register (Ddrpll_Freq5)
Load Synth5 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into DDR Synthesizer5. DDR_MDIV5 0-FFh Synth5 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 288: Video Pll Control Register (Videopll_Ctrl)
VIDEO PLL bypass enable. Normal operation. PLL in bypass mode, reference clock driven at output. Reserved Reserved. Read returns 0. VIDEO_LOC_CTL VIDEO PLL lock output select. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 289: Video Pll Powerdown Register (Videopll_Pwd)
STC0 source0 and STC1 source1). PWD_CLK1 Video PLL Clock1 Powerdown. Setting this bit powers down clock 1 (Source of SYSCLK17 and STC1 source0). Reserved Reserved. Read returns 0. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 290: Video Pll Frequency 1 Register (Videopll_Freq1)
Load Synth1 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into VIDEO Synthesizer1. VID_MDIV1 0-FFh Synth1 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 291: Video Pll Frequency 2 Register (Videopll_Freq2)
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into VIDEO Synthesizer2. VID_MDIV2 0-FFh Synth2 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 292: Video Pll Frequency 3 Register (Videopll_Freq3)
Load Synth3 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into VIDEO Synthesizer3. VID_MDIV5 0-FFh Synth3 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 293: Audio Pll Control Register (Audiopll_Ctrl)
AUDIO PLL bypass enable. Normal operation. PLL in bypass mode, reference clock driven at output. Reserved Reserved. Read returns 0. AUDIO_LOC_CTL AUDIO PLL lock output select. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 294: Audio Pll Powerdown Register (Audiopll_Pwd)
AUDIO PLL Clock3 Powerdown. Setting this bit powers down clock 3 (source clock for SYSCLK20). PWD_CLK2 AUDIO PLL Clock2 Powerdown. Setting this bit powers down clock 2 (source clock for SYSCLK19). Reserved Reserved. Read returns 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 295: Audio Pll Frequency 2 Register (Audiopll_Freq2)
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into AUDIO Synthesizer2. AUD_MDIV2 0-FFh Synth2 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 296: Audio Pll Frequency 3 Register (Audiopll_Freq3)
Load Synth3 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into AUDIO Synthesizer3. AUD_MDIV3 0-FFh Synth3 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 297: Audio Pll Frequency 4 Register (Audiopll_Freq4)
Load Synth4 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into AUDIO Synthesizer4. AUD_MDIV4 0-FFh Synth4 Frequency M Post Divider. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 298: Audio Pll Frequency 5 Register (Audiopll_Freq5)
Load Synth5 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded into AUDIO Synthesizer5. AUD_MDIV5 0-FFh Synth5 Frequency M Post Divider. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 299: Device Configuration Registers
700h USB_CLK_CTL USB Clock Control Register Section 1.16.1.3.35 704h PLL_OBSCLK_CTRL PLL Observe Clock Control Register Section 1.16.1.3.36 70Ch DDR_RCD DDR RCD Register Section 1.16.1.3.37 SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 300: Device Identification Register (Device_Id)
31-28 DEVREV 0-Fh Device revision. 27-12 PARTNUM 0-FFFFh Device part number (unique JTAG ID). 11-1 MFGR 0-7FFh Manufacturer’s JTAG ID. Reserved Reserved. Always 1. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 301: Initiator Pressure 0 Register (Init_Pressure_0)
0-3h System DEMMU initiator pressure. GEM_CFG 0-3h C674x™ CFG port initiator pressure. GEM_MDMA 0-3h C674x™ DMA port initiator pressure. HOST_ARM 0-3h Cortex™-A8 initiator pressure. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 302: Initiator Pressure 1 Register (Init_Pressure_1)
USB_QMGR 0-3h USB Queue Manager initiator pressure. USB_DMA 0-3h USB DMA port initiator pressure. CPGMAC1 0-3h CPGMAC1 initiator pressure. CPGMAC0 0-3h CPGMAC0 initiator pressure. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 303: Mmu Configuration Register (Mmu_Cfg)
MMU operation. Reserved Reserved. Read returns 0. EXPMMU Expansion Slot uses MMU. TC0MMU TPTC0 Uses MMU. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 304: Tptc Configuration Register (Tptc_Cfg)
32 byte 64 byte 128 byte TC2DBS 0-3h TC2 Default Burst Size. TC1DBS 0-3h TC1 Default Burst Size. TC0DBS 0-3h TC0 Default Burst Size. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 305: Ddr Control Register (Ddr_Ctrl)
DDR0 Data Slew. Reflects the DDR0 Data Macro slew adjustment programmed in eFuse. DDRCMD_SLEW0 0-3h DDR0 CMD Slew. Reflects the DDR0 CMD Macro slew adjustment programmed in eFuse. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 306: Dsp Standby/Idle Management Register (Dsp_Idle_Cfg)
Smart-idle wakeup-capable mode: Target acknowledges idle requests after fulfilling IP internal requirements. IRQ/DMA related wake-up events may be generated when in standby. Reserved Reserved. Read returns 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 307: Usb Control Register (Usb_Ctrl)
Normal operating mode. PHYSLEEP0 USB PHY0 sleep mode control Places Phy0 in Sleep mode per USB 2.0 LPM addendum. Sleep mode. Normal operating mode. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 308: Usb Phy Control Register 0 (Usbphy_Ctrl0)
HS Transmit Rise/Fall Time Adjust. 11-8 TXVREFTUNE HS DC Voltage Level Adjust. Reserved Reserved. Read returns 0. TXHSXVTUNE Transmit High-Speed Crossover Adjust. Reserved Reserved. Read returns 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 309: Usb Phy Control Register 1 (Usbphy_Ctrl1)
HS Transmit Rise/Fall Time Adjust. 11-8 TXVREFTUNE HS DC Voltage Level Adjust. Reserved Reserved. Read returns 0. TXHSXVTUNE Transmit High-Speed Crossover Adjust. Reserved Reserved. Read returns 0. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 310: Ethernet Mac Id0 Low Register (Mac_Id0_Lo)
MAC0 Address – Byte 2. 23-16 MACADDR[31:24] 0-FFh MAC0 Address – Byte 3. 15-8 MACADDR[39:32] 0-FFh MAC0 Address – Byte 4. MACADDR[47:40] 0-FFh MAC0 Address – Byte 5. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 311: Ethernet Mac Id1 Low Register (Mac_Id1_Lo)
MAC1 Address – Byte 2. 23-16 MACADDR[31:24] 0-FFh MAC1 Address – Byte 3. 15-8 MACADDR[39:32] 0-FFh MAC1 Address – Byte 4. MACADDR[47:40] 0-FFh MAC1 Address – Byte 5. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 312: Pcie Configuration Register (Pcie_Cfg)
PCIe PLL Status. Reserved Reserved. Read returns 0. PCIE_DEVTYPE PCIe Module Device Type. Endpoint (EP) operation. Legacy Endpoint operation. Root Complex (RC) operation. Reserved. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 313: Clock Control Register (Clk_Ctl)
20-30 MHz 30-40 MHz 40-50 MHz DEVSW1 Device Oscillator Frequency Selection. 5-20 MHz 20-30 MHz 30-40 MHz 40-50 MHz Reserved Reserved. Read returns 0. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 314: Audio Interface Control Register (Aud_Ctrl)
Reserved. Read returns 0. ASP2MUTESRC McASP2 AMUTEIN source select. Use MCA2_AMUTEIN Use MCA0_AMUTEIN ASP1MUTESRC McASP1 AMUTEIN source select. Use MCA1_AMUTEIN. Use MCA0_AMUTEIN. Reserved Reserved. Read returns 0. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 315: Dsp L2 Memory Sleep Mode Register (Dspmem_Sleep)
DSPMEM_DS DSP L2 Memory in Deep Sleep Mode. Memory contents are preserved. DSPMEM_LS DSP L2 Memory in Light Sleep Mode. Memory contents are preserved. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 316: On-Chip Memory Sleep Mode Register (Ocmem_Sleep)
OCM0 Memory in Shutdown Mode. Memory contents are lost. OCM0_DS OCM0 Memory in Deep Sleep Mode. Memory contents are preserved. OCM0_LS OCM0 Memory in Light Sleep Mode. Memory contents are preserved. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 317: Hd Dac Control Register (Hd_Dac_Ctrl)
Normal operation (DSS output). Output calibration value. HD_MIDRND HD DAC MID randomizer mode. Bypass mode. Swap 1. Swap 2. Bit shift. RESET_HD Reset HD DACs SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 318: Hd Dac A Calibration Register (Hd_Daca_Cal)
HD DAC B calibration value. This is driven as a constant value to the DAC when HD_CALSEL in the HD_DAC_CTRL register is set to 1. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 319: Hd Dac C Calibration Register (Hd_Dacc_Cal)
Normal operation (DSS output). Output calibration value. SD_MIDRND SD DAC MID randomizer mode. Bypass mode. Swap 1. Swap 2. Bit shift. RESET_SD Reset SD DACs SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 320: Sd Dac A Calibration Register (Sd_Daca_Cal)
SD DAC B calibration value. This is driven as a constant value to the DAC when SD_CALSEL in the SD_DAC_CTRL register is set to 1. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 321: Sd Dac C Calibration Register (Sd_Dacc_Cal)
SD DAC D calibration value. This is driven as a constant value to the DAC when SD_CALSEL in the SD_DAC_CTRL register is set to 1. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 322: Hw Event Select (Group 1) Register (Hw_Evt_Sel_Grp1)
13-8 EVENT2 0-3Fh Select 2nd trace event from group 1. Reserved Reserved. Read returns 0. EVENT1 0-3Fh Select 1st trace event from group 1. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 323: Hw Event Select (Group 2) Register (Hw_Evt_Sel_Grp2)
13-8 EVENT2 0-3Fh Select 2nd trace event from group 2. Reserved Reserved. Read returns 0. EVENT1 0-3Fh Select 1st trace event from group 2. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 324: Hw Event Select (Group 3) Register (Hw_Evt_Sel_Grp3)
13-8 EVENT2 0-3Fh Select 2nd trace event from group 3. Reserved Reserved. Read returns 0. EVENT1 0-3Fh Select 1st trace event from group 3. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 325: Hw Event Select (Group 4) Register (Hw_Evt_Sel_Grp4)
13-8 EVENT2 0-3Fh Select 2nd trace event from group 4. Reserved Reserved. Read returns 0. EVENT1 0-3Fh Select 1st trace event from group 4. SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 326: Hdmi Observe Clock Control (Hdmi_Obsclk_Ctrl)
10 - 3.5 mA 10 - 3.33 mA 01 - 3.0 mA 01 - 2.66 mA 00 - 2.5 mA 00 - 2.00 mA Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 327: Serdes Control Register (Serdes_Ctrl)
Table 1-232. USB Clock Control Register (USB_CLK_CTL) Field Descriptions Field Value Description 31-2 Reserved Reserved. Read returns 0. (USBSW2,USBSW1) USB Oscillator Frequency Selection. 5-20 MHz 20-30 MHz 30-40 MHz 40-50 MHz SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 328: Pll Observe Clock Control Register (Pll_Obsclk_Ctrl)
Table 1-234. DDR RCD Register (DDR_RCD) Field Descriptions Field Value Description 31-1 Reserved Reserved. Read returns 0. PWRDN Power enable/disable for RCD. Power down. Normal mode. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 329: Interrupt Controller
Cortex A8 SS Interrupts Interrupts SOC Peripherals Internal Internal Interrupt Controller Peripherals Peripherals DSP SS Interrupts Interrupts SOC Peripherals Internal Internal Interrupt Controller Peripherals Peripherals SPRUGX9 – 15 April 2011 Chip Level Resources Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 330: Resets
Refer to the device-specific data manual for Pin Behaviors at Reset. Internal pull-up/down resistors are enabled during and immediately after reset as described in the Terminal Functions section of the data manual. Chip Level Resources SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 331: Dmm/Tiler
This chapter describes the Dynamic Memory Manager (DMM) and its Tiling and Isometric Lightweight Engine for Rotation (TILER) submodule..........................Topic Page ....................Introduction ....................Architecture ......................Use Case ......................Registers SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 332: Introduction
Infrastructure (128-bits wide at 500 MHz) TILER1 TILER2 (128 bits at 400 MHz) ELLA ROBIN1 ROBIN2 EMIF_0 EMIF_1 Device ..DDR Bank 0 DDR Bank 1 DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 333: 2.1.2 Features
Figure 2-2. DMM Block Diagram Slave Ports (From L3 Interconnect) ELLA TILER1 TILER2 LISA ROBIN1 ROBIN2 Master Port Master Port (to EMIF1 SDRAM Controller) (to EMIF2 SDRAM Controller) SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 334: Terminologies And Acronyms Used In This Document
Height and Width information. The DMM-TILER decodes the access type based on the Height, width and address, and responds with read/write from/to data in the physical memory, which has been co-located, with sub-tile granularity. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 335: Architecture
3. ROBIN read data to the relevant TILER initiators or to ELLA initiator. The LISA block registers are DMM_LISA_MAP_i (i = 0 to 3) and DMM_LISA_LOCK. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 336 DMM container that has the same location. For example - The entry (74, 42) in the table corresponds to the page (74, 42) in any DMM container. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 337: Dmm Look-Up Table
32-bit and paged modes can be mapped to their unique System Address, by defining their base addresses. Figure 2-4 describes the actual translation that happens. Figure 2-4. DMM PAT Direct Access Translation Input virtual address CONT_x BASE_ADDR Translated address SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 338: Dmm Pat In-Direct Access Translation
Bits 20:26 - 7 bits, that select vertical page in the tiler container and also Y co-ordinate of the LUT table • Bits 27:31 - In 16 bit mode, their value is binary (01101), that is address in range 6800 0000h-6FFF FFFFh DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 339 The target memory controller: A section may hit either of EMIF banks or both. • Its interleaving definition : Interleave at 128Bytes, 256 Bytes, 512 Bytes or no interleaving. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 340: Dmm Section And Memory Mapping
The interleaving of data between two EMIF banks is transparent to all the initiators of the system and will not require special address conversions. Figure 2-7 Figure 2-8 give examples of all the interleaving schemes. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 341: 512Kb And 1Kb Interleaving
@ 0x400 to 0x5FF @ 0x200 to 0x3FF EMIF0 @ (max_addr + 1) @ 0x0 to max_addr EMIF1 (2 x max_addr + 1) EMIF1 528-byte Interleaving No Interleaving SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 342: Overview Of Request Conversion
Orientation match the orientation Tiled 2D address Byte enable Tiled address Data space Page-based translation Optional Flat physical Physical address Byte enable Data address space DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 343: Memory Map
PAT Indirect access translation, then this 128MB is mapped to any location in the SDRAM, using the LUT tables, at the granularity of 4KB page. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 344 (direct translation and indirect translation) which will be described in PAT section. Note that indirect mode is the most commonly used. Direct mode is used only for debug or in case of a DMM without PAT module. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 345: Dmm Address Translations
32 bits - 1D (or’ physical) address format (PAGE / TILE / SUBTILE / PIXEL structure) The PAGE field is 19 bit wide after PAT processing. A base bit (’b’) has been appended LISA SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 346: Tiler Functional Description
2. Fewer SDRAM page opens. 3. Lesser wastage of memory bandwidth in the system. This concept is the primary motive for storing the image data in the tiled format. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 347: Image Stored In The Memory By Tiler
This section is a synthesis of all TILER concepts, through a top-down approach starting from the main object container, giving one rule per TILER structure level. Figure 2-14 shows the TILER address space structure for tiled modes. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 348: Address Space Structure For Tiled Modes
0-degree view with horizontal mirror 512MiB 180-degree view 512MiB 90-degree view with vertical mirror 512MiB 270-degree view 512MiB 90-degree view 512MiB 90-degree view with horizontal mirror 512MiB DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 349: 4Kb Page, 8-Bit Mode
Page geometry for 8-,16-, and 32-bit views, respectively. Figure 2-15. 4KB Page, 8-bit Mode 1 page TILE 8x8 subtiles 1 subtiles = 4x4 8-bit elements 4x8x2 = 64 pixels = 64 bytes SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 350: 4Kb Page, 16-Bit Mode
Figure 2-17. 4KB Page, 32-bit Mode 1 page 8x8 subtiles 1 subtile = 2x2 32-bit elements 2x8x2 = 32 pixels = 128 bytes (2 rows of 2 32-bit elements) DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 351: Four 1Kb Tiles In One 4Kb Page
Figure 2-18. Four 1KB Tiles in One 4KB Page 255,125 1kiB 1kiB 255,126 1kiB 1kiB 253,127 254,127 255,127 Increasing addresses Memory view Container view Increasing 4-kiB page 1-kiB tile addresses SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 352 Data mapping Sub-tile 8-bit data Figure 2-20. 16-bit Sub-tile 32 bit Increasing addresses Even column sub-tile column sub-tile Container view Memory view Data mapping Sub-tile 16-bit data DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 353 The other LUT would be used to map the 128 MB contained for paged accesses, as shown in Figure 2-24. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 354: Address Format
Incremental bursts - including those issued by a 2D block burst breakdown - are split at: – the interleaving granularity of the section - 128 byte, 256 byte or 512 byte - in interleaved sections – 1-KB boundary in non-interleaved sections DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 355: Tiler Object Containers And Views
TILER base address + 1000 0000h address space 32-bit mode container (128 MiB) TILER base address + 1800 0000h Page mode container (128 MiB) Increasing TILER view Memory mapping addresses SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 356: Using Lut To Translate Tiled Virtual Address To Physical Sdrc Address
Figure 2-25. Object Container Geometry with 4KB Pages 255,123 254,124 255,124 253,125 254,125 255,125 4-kiB page 251,126 252,126 253,126 254,126 255,126 Increasing addresses 249,127 250,127 251,127 252,127 253,127 254,127 255,127 DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 357: Tiler Page Mapping When Using 4Kb
This section describes the eight on-the-fly orientation-related isometric transforms, corresponding to all available changes of orthonormal basis in the TILER container bi-dimensional space. Figure 2-27 shows isometric transforms in the TILER container: SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 358: Isometric Transforms In The Tiler Container
SDRAM memory page • any request that spans over 2 or 4 tiles, is distributed on a maximum number of SDRAM memory controllers DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 359: Paged Mode Addressing
The tiled mode, which defines the considered atomic element size • The orientation, which potentially swaps its x and y axis - and hence the container geometry Table 2-3 summarizes tiled mode container characteristics. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 360: Tiled Mode Addressing In 0° Or 180° Orientations, (S = 0)
32-bit mode: stride_32bitmode = 4 bytes per sub-tile × 2 bytes height of a sub-tile line × 8 sub-tiles per tile × 2 tiles per page × 128 pages = 4 × 2 × 8 × 2 × 128 = 16KB DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 361 In the next sections, the natural container orthonormal basis is referenced as: (Xn , Yn) and the oriented orthonormal basis as: (Xo , Yo). SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 362: Tiled Mode Ordering Of Elements In Natural View
Figure 2-32. Page Mode Ordering of Elements in Natural View 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 1,127 0,127 254,127 255,127 Container view DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 363: Tiled Mode Ordering Of Elements In 0° View With Vertical Mirror
Figure 2-34. Page Mode Ordering of Elements in 0° View with Vertical Mirror 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 364: Tiled Mode Ordering Of Elements In 0° View With Horizontal Mirror
Figure 2-36. Page Mode Ordering of Elements in 0° View with Horizontal Mirror 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 365: Tiled Mode Ordering Of Elements In 180° View
Figure 2-38. Page Mode Ordering of Elements in 180° View 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 366: Tiled Mode Ordering Of Elements In 90º View With Vertical Mirror
Figure 2-40. Page Mode Ordering of Elements in 90º View with Vertical Mirror 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 1,127 0,127 254,127 255,127 Container view DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 367: Tiled Mode Ordering Of Elements In 270° View
Figure 2-42. Page Mode Ordering of Elements in 270° View 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 368: Tiled Mode Ordering Of Elements In 90° View
Figure 2-44. Page Mode Ordering of Elements in 90° View 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 369: Tiled Mode Ordering Of Elements In 90º View With Horizontal Mirror
Figure 2-46. Page Mode Ordering of Elements in 90º View with Horizontal Mirror 254,0 255,0 4-kiB page Natural basis Oriented basis Increasing addresses 0,127 1,127 254,127 255,127 Container view SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 370: Use Case
9000 0000h. Paged mode container will be mapped to 9800 0000h. Configure all initiators to use PAT view 0: Program DMM_PAT_VIEW__0..1 to a value of 0. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 371: Simple Lut Bypass Use Case: Arrangement Of Video Buffers
HD Luma HD Luma Buffer 41 Buffer 48 HD Luma HD Luma Buffer 49 Buffer 56 HD Luma HD Luma 8-bit container 16-bit container Empty space SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 372: Buffer Arrangement For Hd Chroma Buffers In 128Mb 16-Bit Mode Container
NOTE: The above scheme of Luma and Chroma buffer arrangement can be optimized further, by allocating buffers on sub-tile boundary, instead of page boundary (which is required when using LUT for address translation). DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 373: Lut Refill Using The Pat Refill Engines
The PAT descriptor node and the entry data pointer must both be 16-byte aligned. A typical 'C' language description of this node is as follows: struct PAT_desc { struct PAT_desc *next; u32_t area; u32_t ctrl; PAT_data *data; } __attribute__ ((aligned(16))); SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 374: Pat Area Description
(DMM_PAT_CONFIG). Only (x0,y0) is used in direct mode. 3. Select the LUT_ID using DMM_PAT_CTRL__x register. 4. Read (or write) the data in DMM_PAT_DATA__x register. x is the refill engine index. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 375: Dmm Simple Manual Area Refill
DMM_PAT_CTRL_x 0 0 D DMM_PAT_DATA_x ¹ NULL PAT Internal Register Set PAT Physical Address Translation Table Entry 0 Entry 1 Entry 2 ¼ Entry Table 0 SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 376: Dmm Single Auto-Configured Area Refill
0 0 D data: ¹ NULL Memory-mapped descriptor 0 PAT Physical Address Translation Table Entry 0 Entry 1 Entry 2 ¼ Entry Table 0 DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 377: Dmm Chained Auto-Configured Area Refill
Memory-mapped descriptor 0 Memory-mapped descriptor 1 Entry 0 Entry 0 Entry 1 Entry 1 Entry 2 Entry 2 ¼ ¼ Entry Table 0 Entry Table 1 SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 378: Dmm Synchronised Auto-Configured Area Refill
Memory-mapped descriptor 0 Memory-mapped descriptor 1 Entry 0 Entry 0 Entry 1 Entry 1 Entry 2 Entry 2 ¼ ¼ Entry Table 0 Entry Table 1 DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 379: Dmm Cyclic Synchronised Auto-Configured Area Refill
Memory-mapped descriptor 0 Memory-mapped descriptor 1 Entry 0 Entry 0 Entry 1 Entry 1 Entry 2 Entry 2 ¼ ¼ Entry Table 0 Entry Table 1 SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 380: Address Management Using Lisa Sections
SDRC_INTL defines the granularity of the interleaving if the section is mapped on more than one memory controllers A couple of examples are given in the next subsections. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 381: Case 1 Memory Controllers
9. OR upper physical address bits with SDRC_ADDR: 0CD7 1BF0h 10. Physical address: 0CD7 1BF0h This request will be forwarded to address 0CD7 1BF0h, of the second memory controller, that is, EMIF1. SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 382: Case 2 Memory Controllers
9. OR upper physical address bits with SDRC_ADDR: 0011 1A60h 10. Physical address: 0011 1A60h This request will be forwarded to address 0011 1A60h, of the second memory controller; that is, EMIF1. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 383: Dmm Section Use-Case 2
Section 1 64MB EMIF 1 0xC000:0000 Section 0 0x0000:0000 512MB 128MB 0xC7fff:ffff 0x2000:0000 Section 1 64MB 256-byte interleaving between two EMIFs 128-byte interleaving between two EMIFs SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 384: Section Mapping Option
0 (Unused Reserved field) 0 (Unused Reserved field) SDRC_MAP 3h (Map to both EMIF0 and EMIF1) 1 (Map to EMIF0) SDRC_ADDR 0 (SDRC address MSB) 20h (SDRC address MSB) DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 385: Registers
29-28 Reserved Reserved 27-16 FUNC Software compatability level 15-11 RRTL RTL Version (R) 10-8 XMAJOR Major Revision (X) CUSTOM Special DMM version YMINOR Minor Revision (Y) SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 386: Dmm Clock Management Configuration: Dmm_Sysconfig
Table 2-13. DMM_LISA_LOCK Register Field Descriptions Field Value Description Type 31-1 Reserved Reserved LOCK DMM lock map DMM_LISA_MAP__x un-locked No effect (clear on reset only) DMM_LISA_MAP__xlocked Locking DMM_LISA_MAP__x registers DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 387: Dmm Lisa Map Registers: Dmm_Lisa_Map_0-Dmm_Lisa_Map_3
Mapped on SDRC 0 only (not interleaved) Mapped on SDRC 1 only (not interleaved) Mapped on SDRC 0 and SDRC 1 (interleaved) SDRC_ADDR SDRAM controller address MSB SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 388: Dmm Tiler Orientation Registers: Dmm_Tiler_Or0-Dmm_Tiler_Or1
Mode of Refill Engine 2 0 : Normal Mode 1h : Direct LUT access MODE0 Mode of Refill Engine 0 0 : Normal Mode 1h : Direct LUT access DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 389: Dmm_Pat_View Registers
Write-enable for V1 bit-field; V1 field is unchanged Reserved Reserved PAT view for initiator 8.n+1 Write-enable for V0 bit-field; V0 field is unchanged Reserved Reserved PAT view for initiator 8.n+0 SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 390: Dmm_Pat_View_Map Registers
Direct access, container base address given in CONT_8 indirect access through the LUT indexed by CONT_8 Reserved Reserved CONT_8 Base address of Container for 8-bit mode -or - LUT index DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 391: Dmm_Pat_View_Map_Base Register
End of refill event for the last descriptor in area 3 R/W1S FILL_DSC3 End of refill event for any descriptor in area 3 R/W1S ERR_LUT_MISS2 Unexpected Access to a yet-to-be-refilled area event in area 2 R/W1S SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 392 R/W1S FILL_LST0 End of refill event for the last descriptor in area 0 R/W1S FILL_DSC0 End of refill event for any descriptor in area 0 R/W1S DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 393: Dmm_Pat_Irqstatus_Raw Register
End of refill event for the last descriptor in area 1 R/W1S FILL_DSC1 End of refill event for any descriptor in area 1 R/W1S ERR_LUT_MISS0 Unexpected Access to a yet-to-be-refilled area event in area 0 R/W1S SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 394 R/W1S FILL_LST0 End of refill event for the last descriptor in area 0 R/W1S FILL_DSC0 End of refill event for any descriptor in area 0 R/W1S DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 395: Dmm_Pat_Irqstatus Register
End of refill event for any descriptor in area 1 R/W1C ERR_LUT_MISS0 Unexpected Access to a yet-to-be-refilled area event in area 0 R/W1C ERR_UPD_DATA0 Data register update whilst refilling error event in area 0 R/W1C SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 396 R/W1C FILL_LST0 End of refill event for the last descriptor in area 0 R/W1C FILL_DSC0 End of refill event for any descriptor in area 0 R/W1C DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 397: Dmm_Pat_Irqenable_Set Register
End of refill event for any descriptor in area 1 R/W1S ERR_LUT_MISS0 Unexpected Access to a yet-to-be-refilled area event in area 0 R/W1S ERR_UPD_DATA0 Data register update whilst refilling error event in area 0 R/W1S SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 398 R/W1S FILL_LST0 End of refill event for the last descriptor in area 0 R/W1S FILL_DSC0 End of refill event for any descriptor in area 0 R/W1S DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 399: Dmm_Pat_Irqenable_Clr Register
End of refill event for any descriptor in area 1 R/W1C ERR_LUT_MISS0 Unexpected Access to a yet-to-be-refilled area event in area 0 R/W1C ERR_UPD_DATA0 Data register update whilst refilling error event in area 0 R/W1C SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 400 R/W1C FILL_LST0 End of refill event for the last descriptor in area 0 R/W1C FILL_DSC0 End of refill event for any descriptor in area 0 R/W1C DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 401: Dmm_Pat_Status Registers
Area reloading finished for engine n Area currently reloading for engine n VALID Valid area description for engine n READY Area registers ready for engine n SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 402: Dmm_Pat_Descr Registers
X-coordinate of the bottom right corner of the area Reserved Reserved 14-8 Y-coordinate of the top left corner of the PAT area X-coordinate of the top left corner of the PAT area DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 403: Dmm_Pat_Ctrl Registers
Field Value Description Type 31-4 ADDR Physical address of the current table refill entry data or single actual entry data when in manual mode Reserved Reserved SPRUGX9 – 15 April 2011 DMM/TILER Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 404: Dmm_Peg_Prio Registers
Table 2-31. DMM_PEG_PRIO_PAT Register Field Descriptions Field Value Description Type 31-4 Reserved Reserved W_PAT Write-enable for P_PAT bit-field; P_PAT field is updated P_PAT Priority for PAT engine. DMM/TILER SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 405 ........................... Topic Page ....................Introduction ....................Architecture ......................Registers SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 406 Configurable receive address matching/filtering, receive FIFO depth, and transmit FIFO depth • No-chain mode truncates frame to first buffer for network analysis applications • Emulation support • Loopback mode EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 407: 3.1.4 Emac And Mdio Block Diagram
The EMAC and MDIO interrupts are combined into a single interrupt within the control module. The interrupt from the control module then goes to the ARM interrupt controller. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 408 (also known as a switch) with a dedicated LAN connecting each bridge port to a single device. Full-duplex operation constitutes a proper subset of the MAC functionality required for half-duplex operation. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 409: Physical Layer Definitions
A cable element that consists of two insulated conductors twisted together in a regular fashion to form a balanced transmission line. Port— Ethernet device. Promiscuous Mode— EMAC receives frames that do not match its address. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 410 However, the EMAC throughput is better when the descriptors are placed in the local EMAC RAM. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 411: Ethernet Configuration-Gmii Connections
2.5 MHz, EMAC_TXD[0-7] 25 MHz, or 125 MHz EMAC_TXEN EMAC_COL Physical layer EMAC_CRS System device core (PHY) EMAC_RXCLK Transformer EMAC_RXD[0-7] EMAC_RXDV EMAC_RXER RJ−45 MDIO_MCLK MDIO_MDIO SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 412: Emac And Mdio Signals For Gmii Interface
PHY address, register address, and data bit cycles. The MDIO_MDIO pin acts as an output for everything except the data bit cycles, when the pin acts as an input for read operations. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 413: Ethernet Frame Format
60 to (RXMAXLEN - 4) bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 414: Basic Descriptor Format
3-5. Figure 3-4. Basic Descriptor Format Bit Fields Word Offset 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Buffer Length Flags Packet Length 414 EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 415: Typical Descriptor Linked List
502 bytes −−− −−− pNext Packet B pBuffer Fragment 3 500 bytes −−− pNext (NULL) pBuffer Packet C 1514 1514 bytes SOP | EOP 1514 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 416 HDP that started the process. This process applies when adding packets to a transmit list, and empty buffers to a receive list. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 417 EMAC. This mechanism ensures that the application software never misses an EMAC interrupt, since the interrupt and its acknowledgment are tied directly to the actual buffer descriptors processing. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 418: Transmit Buffer Descriptor Format
Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */ } EMAC_Desc; /* Packet Flags */ #define EMAC_DSC_FLAG_SOP 0x80000000u #define EMAC_DSC_FLAG_EOP 0x40000000u #define EMAC_DSC_FLAG_OWNER 0x20000000u #define EMAC_DSC_FLAG_EOQ 0x10000000u #define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u #define EMAC_DSC_FLAG_PASSCRC 0x04000000u EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 419 EOP flag. This bit is set by the software application and is not altered by the EMAC. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 420 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 421: Receive Buffer Descriptor Format
The software application must set this value prior to adding the descriptor to the active receive list. This pointer is not altered by the EMAC. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 422 The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 423 This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 424 EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 425: Emac Control Module Block Diagram
To arbitrate between the CPU and EMAC buses for access to internal descriptor memory. • To arbitrate between internal EMAC buses for access to system memory. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 426: Emac Control Module Interrupts
4. Write the MAC end of interrupt vector register (MACEOIVECTOR) in the EMAC module with a value of 1h to signal the end of the receive interrupt processing. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 427 2 and 63 inclusive, indicating the target number of interrupts per 1 ms going to the CPU. Similarly, the number of receive interrupt pulses to the CPU is also separately controlled. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 428: Mdio Module Block Diagram
The module tracks whether or not a PHY on a particular address has responded, and whether or not the PHY currently has a link. Using this information allows the software application to quickly determine which MDIO address the PHY is using. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 429 USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 430 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 431 MDIO_REGS->USERACCESS0 = CSL_FMK(MDIO_USERACCESS0_GO,1u) CSL_FMK(MDIO_USERACCESS0_WRITE,1) CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) CSL_FMK(MDIO_USERACCESS0_DATA, data) #define PHYREG_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ) #define PHYREG_waitResults( results ) { while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); } SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 432: Emac Module Block Diagram
The receive FIFO consists of 68 cells of 64 bytes each and associated control logic. The FIFO buffers receive data in preparation for writing into packet buffers in device memory, and also enable receive FIFO flow control. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 433 3.2.8.1.12 Clock and Reset Logic The clock and reset submodule generates all the EMAC clocks and resets. For more details on reset capabilities, see Section 10.2.9.1. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 434 The EMAC keeps track of 36 different statistics, plus keeps the status of each individual packet in its corresponding packet descriptor. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 435 Receive flow control is enabled by the RXBUFFERFLOWEN bit and the RXFIFOFLOWEN bit in MACCONTROL. The FULLDUPLEX bit in MACCONTROL configures the EMAC for collision or IEEE 802.3X flow control. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 436 If the RXBUFFERFLOWEN bit in MACCONTROL is cleared to 0 while the pause time is nonzero, then the pause time is cleared to 0 and a zero count pause frame is sent. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 437 96 bit times (approximately, but not less) is measured from MCRS. 3.2.9.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 438 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 439 If a multicast packet does not hash match, regardless of whether or not hash matching is enabled, but matches an enabled multicast address in the RAM, then the packet will be transferred to the associated channel. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 440 QOS or receive flow control is used. Disabled channel free buffer values are do not cares. During initialization, the host should write the number of free buffers for each enabled channel EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 441 If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last data byte. 3.2.10.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receive SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 442: Receive Frame Treatment Summary
No undersized/fragment frames are transferred. All address matching frames with and without errors transferred to the address match channel 442 EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 443: Middle Of Frame Overrun Treatment
OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 444 1536 packet bytes). Cell transmission can be configured to start only after an entire packet is contained in the FIFO; for a maximum-size packet, set the TXCELLTHRESH field to the maximum possible value of EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 445 After a software reset operation, all the EMAC registers need to be reinitialized for proper data transmission. Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register inside their memory map. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 446 Once the interrupt is mapped to a CPU interrupt, general masking and unmasking of the interrupt (to control reentrancy) should be done at the chip level by manipulating the interrupt enable mask. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 447 [Discussed later in this document] /* Enable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.CMRXINTEN = 0xff; EmacControlRegs->CONTROL.C_TX_EN = 0xff; EmacControlRegs->CONTROL.CMRXTHRESHINTEN = 0xff; EmacControlRegs->CONTROL.C_MISC_EN = 0xf; SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 448 Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 449 TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL. 18. Enable the device interrupt in the EMAC control module interrupt control registers (CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 450: Emac Control Module Interrupt Logic Diagram
The transmit DMA engine has eight channels, with each channel having a corresponding interrupt (TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 451 The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 452 Zero buffer length • Packet length error The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 453 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT, and USERINT. For more details on the ARM interrupt controller (AINTC), see the SoC Subsystem Reference Guide. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 454 SOFT and FREE bits affect the operation of the emulation suspend. Table 3-8. Emulation Control SOFT FREE Description Normal operation Emulation suspend Normal operation EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 455: Emac/Mdio Registers
Section 3.3.1.11 CMMISCINTSTAT Miscellaneous Interrupt Status Register Section 3.3.1.12 CMRXINTMAX Receive Interrupts Per Millisecond Register Section 3.3.1.13 CMTXINTMAX Transmit Interrupts Per Millisecond Register Section 3.3.1.14 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 456: Emac Control Module Identification And Version Register (Cmidver)
Software reset – Writing a one to this bit causes the CPGMACSS_S logic to be reset (INT, REGS, CPPI). Software reset occurs on the clock following the register bit write. No software reset. Software reset occurs. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 457: Emac Control Module Emulation Control Register (Cmemcontrol)
Free-running mode is disabled. During emulation halt, SOFT bit determines operation of the EMAC control module. Free-running mode is enabled. During emulation halt, the EMAC control module continues to operate. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 458: Emac Control Module Interrupt Control Register (Cmintctrl)
C2_RX : Enables C2_Rx_Pulse Pacing C2_TX : Enables C2_Tx_Pulse Pacing 15-12 Reserved Reserved. 11-0 INTPRESCALE 0-7FFh Interrupt Counter Prescaler – The number of VBUSP_CLK periods in 4 μs. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 459: Emac Control Module Receive Threshold Interrupt Enable Register (Cmrxthreshinten)
Core 0 Receive Enable. Each bit in this register corresponds to the bit in the RX interrupt that is enabled to generate an interrupt on C0_RX_PULSE. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 460: Emac Control Module Transmit Interrupt Enable Register (Cmtxinten)
Core 0 Misc Enable Each bit in this register corresponds to the miscellaneous interrupt (STAT_PEND, HOST_PEND, MDIO_LINKINT, MDIO_USERINT) that is enabled to generate an interrupt on C0_Misc_PULSE. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 461: Emac Control Module Receive Threshold Interrupt Status Register (Cmrxthreshintstat)
Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on C0_RX_THRESH_PULSE. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 462: Emac Control Module Receive Interrupt Status Register (Cmrxintstat)
Core 0 Transmit Masked Interrupt Status. Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on C0_TX_PULSE. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 463: Emac Control Module Miscellaneous Interrupt Status Register (Cmmiscintstat)
Core 0 Misc Masked Interrupt Status. Each bit in this register corresponds to the miscellaneous interrupt (STAT_PEND, HOST_PEND, MDIO_LINKINT, MDIO_USERINT) that is enabled and generating an interrupt on C0_MISC_PULSE. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 464: Emac Control Module Receive Interrupts Per Millisecond Register (Cmrxintmax)
C_TX_IMAX 0-3Fh Core 0 Transmit Interrupts per Millisecond. The maximum number of interrupts per millisecond generated on C0_TX_PULSE if pacing is enabled for this interrupt. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 465: 3.3.2 Ethernet Media Access Controller (Emac) Registers
Receive Channel 6 Free Buffer Count Register Section 3.3.2.28 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 3.3.2.28 160h MACCONTROL MAC Control Register Section 3.3.2.29 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 466 Receive Channel 3 Completion Pointer Register Section 3.3.2.49 670h RX4CP Receive Channel 4 Completion Pointer Register Section 3.3.2.49 674h RX5CP Receive Channel 5 Completion Pointer Register Section 3.3.2.49 466 EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 467 Receive FIFO or DMA Start of Frame Overruns Register Section 3.3.2.50.34 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 3.3.2.50.35 28Ch RXDMAOVERRUNS Receive DMA Overruns Register Section 3.3.2.50.36 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 468: Transmit Identification And Version Register (Txidver)
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 3-27. Transmit Control Register (TXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved TXEN Transmit enable Transmit is disabled. Transmit is enabled. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 469: Transmit Teardown Register (Txteardown)
Teardown transmit channel 1 Teardown transmit channel 2 Teardown transmit channel 3 Teardown transmit channel 4 Teardown transmit channel 5 Teardown transmit channel 6 Teardown transmit channel 7 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 470: Receive Identification And Version Register (Rxidver)
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 3-30. Receive Control Register (RXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved RXEN Receive enable Receive is disabled. Receive is enabled. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 471: Receive Teardown Register (Rxteardown)
Teardown receive channel 1 Teardown receive channel 2 Teardown receive channel 3 Teardown receive channel 4 Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 472: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)
TX3PEND raw interrupt read (before mask) TX2PEND TX2PEND raw interrupt read (before mask) TX1PEND TX1PEND raw interrupt read (before mask) TX0PEND TX0PEND raw interrupt read (before mask) EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 473: Transmit Interrupt Status (Masked) Register (Txintstatmasked)
TX4PEND TX4PEND masked interrupt read TX3PEND TX3PEND masked interrupt read TX2PEND TX2PEND masked interrupt read TX1PEND TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 474: Transmit Interrupt Mask Set Register (Txintmaskset)
Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 475: Transmit Interrupt Mask Clear Register (Txintmaskclear)
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 476: Mac Input Vector Register (Macinvector)
End of interrupt processing for Miscellaneous interrupt. TXEOI End of interrupt processing for TXPULSE interrupt. RXEOI End of interrupt processing for RXPULSE interrupt. RXTHRESHEOI End of interrupt processing for RXTHRESH interrupt. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 477: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)
RX3PEND raw interrupt read (before mask) RX2PEND RX2PEND raw interrupt read (before mask) RX1PEND RX1PEND raw interrupt read (before mask) RX0PEND RX0PEND raw interrupt read (before mask) SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 478: Receive Interrupt Status (Masked) Register (Rxintstatmasked)
RX4PEND RX4PEND masked interrupt read RX3PEND RX3PEND masked interrupt read RX2PEND RX2PEND masked interrupt read RX1PEND RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 479: Receive Interrupt Mask Set Register (Rxintmaskset)
Receive channel 1 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. RX0MASK Receive channel 0 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 480: Receive Interrupt Mask Clear Register (Rxintmaskclear)
Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. RX0MASK Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 481: Mac Interrupt Status (Unmasked) Register (Macintstatraw)
Table 3-43. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions Field Value Description 31-2 Reserved Reserved HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read STATPEND Statistics pending interrupt (STATPEND); masked interrupt read SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 482: Mac Interrupt Mask Set Register (Macintmaskset)
Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 483: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)
UNDERSIZE bit set in their EOP buffer descriptor. Fragments are short frames that contain CRC / align / code errors and undersized are short frames without errors. Short frames are filtered. Short frames are transferred to memory. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 484 RX multicast enable. Enable received hash matching multicast frames to be copied to the channel selected by RXMULTCH bits. Multicast frames are filtered. Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 485 Select channel 4 to receive multicast frames Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 486: Receive Unicast Enable Set Register (Rxunicastset)
May be read. RXCH0EN Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May be read. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 487: Receive Unicast Clear Register (Rxunicastclear)
Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. RXCH0EN Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 488: Receive Maximum Length Register (Rxmaxlen)
15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 489: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)
Reserved Reserved RXnFLOWTHRESH 0-FFh Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 490: Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
The host must write this field with the number of buffers that have been freed due to host processing. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 491: Mac Control Register (Maccontrol)
Gigabit mode is disabled; 10/100 mode is in operation. Gigabit mode is enabled (full-duplex only). TXPACE Transmit pacing enable bit. Transmit pacing is disabled. Transmit pacing is enabled. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 492 Full-duplex mode. The gigabit mode (GIG = 1) forces full-duplex mode regardless of the FULLDUPLEX bit setting. Half-duplex mode is enabled. Full-duplex mode is enabled. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 493: Mac Status Register (Macstatus)
The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require hardware reset in order to recover. No error Ownership bit not set in SOP buffer Zero buffer pointer Reserved Reserved SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 494 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 495: Emulation Control Register (Emcontrol)
FIFO. This value must be greater than or equal to 2 and less than or equal to 24 (2 ≥ TXCELLTHRESH ≤ 24). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 496: Mac Configuration Register (Macconfig)
If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred. A software reset has not occurred. A software reset has occurred. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 497: Mac Source Address Low Bytes Register (Macsrcaddrlo)
MAC source address bits 31-24 (byte 3) 15-8 MACSRCADDR4 0-FFh MAC source address bits 39-32 (byte 4) MACSRCADDR5 0-FFh MAC source address bits 47-40 (byte 5) SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 498: Mac Hash Address Register 1 (Machash1)
Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 499: Back Off Random Number Generator Test Register (Bofftest)
IPG time is not stretched to four times the normal value. Transmit pacing helps reduce capture effects, which improves overall network bandwidth. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 500: Receive Pause Timer Register (Rxpause)
The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented at slot time intervals down to 0, at which time EMAC transmit frames are again enabled. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 501: Mac Address Low Bytes Register (Macaddrlo)
MATCHFILT bit is cleared to 0. 15-8 MACADDR0 0-FFh MAC address lower 8 bits (byte 0) MACADDR1 0-FFh MAC address bits 15-8 (byte 1) SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 502: Mac Address High Bytes Register (Macaddrhi)
53-bit indexed RAM location is written when the low location is written. All 32 address RAM locations must be initialized prior to enabling packet reception. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 503: Transmit Channel N Dma Head Descriptor Pointer Register (Txnhdp)
Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 504: Transmit Channel N Completion Pointer Register (Txncp)
The EMAC uses the value written to determine if the interrupt should be deasserted. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 505: Statistics Register
Had no CRC error, alignment error, or code error Section 3.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 506 Overruns have no effect on this statistic. CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 507 Was not the result of a collision caused by half duplex, collision based flow control Section 3.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 508 Had no CRC error, alignment error, or code error Section 3.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 509 Experienced no collisions before being successfully transmitted • Found the medium busy when transmission was first attempted, so had to wait. CRC errors have no effect on this statistic. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 510 Experienced 16 collisions before abandoning all attempts at transmitting the frame. None of the collisions were late. CRC errors have no effect on this statistic. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 511 CRC errors, alignment/code errors, and overruns do not affect the recording of frames in this statistic. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 512 Did not experience late collisions, excessive collisions, underrun, or carrier sense error • Was 1024-bytes to RXMAXLEN-bytes long CRC/alignment/code errors, underruns, and overruns do not affect frame recording in this statistic. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 513 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 514: Mdio Version Register (Version)
Description 31-16 MODID 0-FFFFh Identifies type of peripheral. 15-8 REVMAJ 0-FFh Management Interface Module major revision value. REVMIN 0-FFh Management Interface Module minor revision value. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 515: Mdio Control Register (Control)
Clock Divider bits. This field specifies the division ratio between the peripheral clock and the frequency of MCLK. MCLK is disabled when CLKDIV is set to 0. MCLK frequency = peripheral clock frequency/(CLKDIV + 1). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 516: Phy Acknowledge Status Register (Alive)
The PHY indicates it does not have a link or fails to acknowledge the read transaction. The PHY with the corresponding address has a link and the PHY acknowledges the read transaction. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 517: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)
No MDIO link change event. An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register n (USERPHYSELn). SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 518: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register n (USERPHYSELn) and the LINKINTENB bit in USERPHYSELn is set to 1. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 519: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)
USERACCESS1, respectively. Writing a 1 will clear the event and writing a 0 has no effect. No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register n (USERACCESSn) has completed. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 520: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)
The previously scheduled PHY read or write command using MDIO user access register n (USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 521: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)
MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are disabled. MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are enabled. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 522: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)
MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are enabled. MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are disabled. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 523: Mdio User Access Register 0 (Useraccess0)
PHY address bits. This field specifies the PHY to be accessed for this transaction. 15-0 DATA 0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 524: Mdio User Phy Select Register 0 (Userphysel0)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved Reserved. PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 525: Mdio User Access Register 1 (Useraccess1)
PHY address bits. This field specifies the PHY to be accessed for this transaction. 15-0 DATA 0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUGX9 – 15 April 2011 EMAC/MDIO Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 526: Mdio User Phy Select Register 1 (Userphysel1)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved Reserved. PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 527 SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface This chapter describes the general-purpose I/O (GPIO) interface......................... Topic Page ....................Introduction ....................Architecture ....................Registers SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 528 The module provides an alternative to the atomic ‘Test and Set’ operations for the data output and interrupt enable registers. For these registers, the module implements the “Set and Clear protocol register update”. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 529: Gpio Block Diagram
Active mode level detection Debouncing register 1 Interrupt Active mode edge detection OR32 Interrupt status request 2 register 2 Debouncing enable Edge detection control Interrupt enable2 SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 530 When N is between 2 to 8, this logic is running at the equivalent frequency of interface clock frequency divided by N. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 531 For instance, interrupt generation on both edges on input k is configured by setting to 1 the kth bit in registers GPIO_RISINGDETECT and GPIO_FALLINGDETECT along with the interrupt enabling for one or both interrupt lines (GPIO_IRQSTATUS_SET_n). SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 532: Interrupt Request Generation
GPIO line(i) in input detection logic Interrupt request line 1 or 2 Status(i) Status(i+1) Status(31) Interrupt Status Register 1 or 2 GPIO1 to GPIO General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 533 Therefore, for these registers, three addresses are defined for one unique physical register. Reading these addresses has the same effect and returns the register value. SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 534: Write @ Gpio_Cleardataout Register Example
1; a written bit at 0 has no effect. • A read of the set data output register returns the value of the data output register. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 535: Write @ Gpio_Setirqenablex Register Example
This register represents the number of the clock cycle(s) (one cycle is 31 microseconds long) to be used. The following formula describes the required input stable time to be propagated to the debounced output: SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 536: General-Purpose Interface Used As A Keyboard Interface
Figure 4-6. General-Purpose Interface Used as a Keyboard Interface Device ..Keyboard matrix pads channels ..interconnect Interrupt generation Column channels General Purpose Interface General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 537: Gpio Registers
154h GPIO_DEBOUNCINGTIME Debouncing Time Register Section 4.3.18 190h GPIO_CLEARDATAOUT Clear Data Output Register Section 4.3.19 194h GPIO_SETDATAOUT Set Data Output Register Section 4.3.20 SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 538: 4.3.1 Gpio_Revision Register
15-11 0-1Fh RTL version 10-8 MAJOR 0-7h Major Revision CUSTOM 0-3h Indicates a special version for a particular device. MINOR 0-3Fh Minor Revision General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 539: 4.3.2 Gpio_Sysconfig Register
AUTOIDLE Internal interface clock gating strategy Internal Interface OCP clock is free-running Automatic internal OCP clock gating, based on the OCP interface activity SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 540: 4.3.3 Gpio_Eoi Register
Write 0 EOI for interrupt output line #0 Write 1 EOI for interrupt output line #1 Read 0 Reads always 0 (no EOI memory) General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 541: 4.3.4 Gpio_Irqstatus_Raw_N Register
LEGEND: R/W = Read/Write; W1C = Write a 1 to clear to 0, a write of 0 has no effect; -n = value after reset Table 4-6. GPIO_IRQSTATUS_n Register Field Descriptions Bits Field Value Description 31-0 INTLINE[n] Interrupt n status. No effect IRQ is triggered. SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 542: 4.3.6 Gpio_Irqstatus_Set_N Register
LEGEND: R/W = Read/Write; -n = value after reset Table 4-8. GPIO_IRQSTATUS_CLR_n Register Field Descriptions Bits Field Value Description 31-0 INTLINE[n] Interrupt n enable No effect Disable IRQ generation. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 543: 4.3.8 Gpio_Sysstatus Register
LEGEND: R = Read only; -n = value after reset Table 4-9. GPIO_SYSSTATUS Register Field Descriptions Field Value Description 31-1 Reserved Reserved RESETDONE Reset status information. Internal Reset is on-going Reset completed SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 544: 4.3.9 Gpio_Ctrl Register
31-0 OUTPUTEN[n] Output Data Enable The corresponding GPIO port is configured as an output. The corresponding GPIO port is configured as an input. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 545: 4.3.11 Gpio_Datain Register
LEGEND: R/W = Read/Write; -n = value after reset Table 4-13. GPIO_DATAOUT Register Field Descriptions Bits Field Value Description 31-0 DATAOUT 0-FFFF FFFFh Data to set on output pins SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 546: 4.3.13 Gpio_Leveldetect0 Register
Field Value Description 31-0 LEVELDETECT1[n] High Level Interrupt Enable Disable the IRQ assertion on high-level detect. Enable the IRQ assertion on high-level detect. General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 547: 4.3.15 Gpio_Risingdetect Register
Table 4-17. GPIO_FALLINGDETECT Register Field Descriptions Bits Field Value Description 31-0 FALLINGDETECT[n] Falling Edge Interrupt Enable Disable IRQ on falling-edge detect. Enable IRQ on falling-edge detect. SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 548: 4.3.17 Gpio_Debouncenable Register
Value Description 31-8 Reserved Reserved DEBOUNCETIME 0-FFh Input Debouncing Value in 31 microsecond steps. Debouncing time = (DEBOUNCETIME + 1) × 31 microseconds General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 549: 4.3.19 Gpio_Cleardataout Register
Table 4-21. GPIO_SETDATAOUT Register Field Descriptions Bits Field Value Description 31-0 INTLINE [n] Set Data Output Register No effect Set the corresponding bit in the GPIO_DATAOUT register. SPRUGX9 – 15 April 2011 General-Purpose I/O (GPIO) Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 550 General-Purpose I/O (GPIO) Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 551 This chapter describes the general-purpose memory controller (GPMC)......................... Topic Page ....................Introduction ....................Architecture ................Basic Programming Model ..................Use Cases And Tips ....................Registers SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 552 Address decoder, GPMC configuration, and chip-select configuration register file • Access engine • Prefetch and write-posting engine • Error correction code engine (ECC) • External device/memory port interface General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 553: Gpmc Block Diagram
Chip-select Address configuration CS selection Access engine FIFO Data Address Prefetch and write- posting engine Control NAND access only External memory port interface SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 554: Gpmc I/O Description
Not Used GPMC_A[15] Not Used Not Used Not Used GPMC_A[14] Not Used Not Used Not Used GPMC_A[13] Not Used Not Used Not Used 554 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 555 Multiplexing mode can be selected through the GPMC_CONFIG1_i[9-8] MUXADDDATA bit field (i = 0 to 7). • Asynchronous page mode is not supported for multiplexed address and data devices. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 556: Gpmc To 16-Bit Address/Data-Multiplexed Memory
A[27:17] gpmc_d[15:0] A[16:1]/D[15:0] A/D[15:0] gpmc_ncs[7:0] nCS[7:0] gpmc_nadv_ale nADV/ALE nADV gpmc_noe nOE/nRE gpmc_nwe gpmc_nbe0_cle nBE0/CLE nBE0/CLE gpmc_nbe1 nBE1 nBE1 gpmc_nwp gpmc_wait[1:0] WAIT[1:0] WAIT gpmc_clk General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 557: Gpmc To 16-Bit Nonmultiplexed Memory
GPMC memory gpmc_d[7:0] D[7:0] D[7:0] gpmc_ncs[7:0] nCS[7:0] nADV/ALE gpmc_nadv_ale nADV/ALE gpmc_noe nOE/nRE nOE/nRE gpmc_nwe nBE0/CLE gpmc_nbe0_cle gpmc_nbe1 nBE1 gpmc_nwp gpmc_wait[1:0] WAIT[1:0] WAIT gpmc_clk SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 558: 5.2.3 Gpmc Integration
GPMC_FCLK prcm_gpmc_clk bootwaiten ALW_DOM_RST_N GPMC_RST bootwaitselect Table 5-3. GPMC Integration Attributes Attributes Module Instance Power Domain Wake-up Capability Interconnect GPMC ALWAYS_ON L3_Slow General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 559: Gpmc Clocks And Resets
Most GPMC external interface control-signal assertion and deassertion times • Data-capture time during read access • External wait-pin monitoring time • Duration of idle time between accesses, when required SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 560: Gpmc Clocks
Clock Activity Feature not available Master Standby Modes Feature not available Global Wake-up Enable Feature not available Wake-up Sources Enable Feature not available General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 561: Gpmc Interrupt Events
Bursts larger than the memory page length are chopped into multiple bursts transactions. Due to the alignment requirements, a page boundary is never crossed. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 562 After the chip-select is configured, the access engine accesses the external device, drives the external interface control signals, and applies the interface protocol based on user-defined timing parameters and settings. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 563: Chip-Select Address Mapping And Decoding Mask
Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 564 The GPMC_CONFIG1_i[17-16] WAITPINSELECT bit field (where i = 0 to 7) selects which input gpmc_wait pin is used for the device attached to the corresponding chip-select. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 565 GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Figure 5-7 shows wait behavior during an asynchronous single read access. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 566: Wait Behavior During An Asynchronous Single Read Access (Gpmcfclkdivider = 1)
All signals, including the data bus, are controlled according to their related control timing value and to the CYCLETIME counter status. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 567 CYCLETIME counter status. Figure 5-8 shows wait behavior during a synchronous read burst access. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 568: Wait Behavior During A Synchronous Read Burst Access
At WRACCESSTIME completion if WAITMONITORINGTIME = 0 • In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before WRACCESSTIME completion if WAITMONITORINGTIME not equal to 0. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 569 Another way to prevent bus contention is to define an earlier CS or OE deassertion time for slow devices or to extend the value of RDCYCLETIME. Doing this prevents bus contention, but affects all accesses of this specific chip-select. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 570: Read To Read For An Address-Data Multiplexed Device, On Different Cs, Without Bus Turnaround
Figure 5-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround A[16:1]/D[15:0] DATA 0 ADD 1 OEOFFTIME RDCYCLETIME RD/WRCYCLETIME CSOFFTIME nCS0 BUSTURNAROUND nCS1 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 571: Read To Read / Write For A Address-Data Or Aad-Multiplexed Device, On Same Cs, With Bus Turnaround
CYCLE2CYCLEDELAY inactive cycles is inserted between the access being initiated to this chip-select and the previous access ending for a different chip-select. This applies to any type of access (read or write). SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 572: Idle Cycle Insertion Configuration
TIMEPARAGRANULARITY bit (where i stands for the GPMC chip-select value, i = 0 to 7). Increasing all access timing parameters allows support of slow devices. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 573 1KB. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 574 The GPMC_CONFIG2_i[12-8] CSRDOFFTIME (read access) and GPMC_CONFIG2_i[20-16] CSWROFFTIME (write access) bit fields define the CS signal deassertion time relative to start access time. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 575 ADVONTIME, ADVRDOFFTIME, ADVWROFFTIME, and ADVAADMUXRDOFFTIME, ADVAADMUXWROFFTIME usage for CLE and ALE (Command / Address Latch Enable) usage for a NAND Flash interface. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 576 This implies the need to program the WRCYCLETIME bit field to be greater than the WE signal-deassertion time, including the extra half-GPMC_FCLK-period delay. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 577 GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge corresponding to the GPMC_CLK rising edge used for the first data capture. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 578 After a write access, if no other access is pending, the GPMC keeps driving the data bus after WRCYCLETIME completes with the same data to prevent bus floating and power consumption. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 579 Asynchronous multiple (page) read operation on a non-multiplexed device In asynchronous operations GPMC_CLK is not provided outside the GPMC and is kept low. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 580: 5.2.4.10.1.1.1 Asynchronous Single-Read Operation On An Address/Data Multiplexed Device
Address valid signal ADV – ADV assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field. – ADV deassertion time is controlled by the GPMC_CONFIG3_i[[12-8] ADVRDOFFTIME field. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 581: Two Asynchronous Single Read Accesses On An Address/Data Multiplexed Device (32-Bit Read Split Into 2 × 16-Bit Read)
Valid address 1 A[16:1]/D[15:0] Data 1 Data 1 nBE1/nBE0 CSRDOFFTIME CSRDOFFTIME CSONTIME CSONTIME ADVRDOFFTIME ADVRDOFFTIME ADVONTIME ADVONTIME nADV OEOFFTIME OEOFFTIME OEONTIME OEONTIME WAIT SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 582: 5.2.4.10.1.1.4 Asynchronous Single Write On An Address/Data-Multiplexed Device
Write multiple access in asynchronous mode is not supported. If WRITEMULTIPLE is enabled with WRITETYPE as asynchronous, the GPMC processes single asynchronous accesses. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 583 Valid Address A[16:1]/D[15:0] MSB Address LSB Add Data 0 Data 0 nBE1/nBE0 CSRDOFFTIME CSONTIME ADVRDOFFTIME ADVONTIME ADVAADMUXRDOFFTIME ADVAADMUXONTIME nADV OEOFFTIME OEONTIME OEAADMUXOFFTIME OEAADMUXONTIME WAIT SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 584: 5.2.4.10.1.2.2 Asynchronous Single Read On An Aad-Multiplexed Device
– OE second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field. – OE second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 585: Asynchronous Single Write On An Aad-Multiplexed Device
A[27:17] Valid Address WRDATAONADMUXBUS A[16:1]/D[15:0] MSB Address LSB Address Data nBE1/nBE0 CSWROFFTIME CSONTIME ADVWROFFTIME ADVONTIME ADVAADMUXWROFFTIME ADVAADMUXONTIME nADV OEAADMUXOFFTIME OEAADMUXONTIME WEOFFTIME WEONTIME WAIT SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 586 The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field specifies that the GPMC_CLK is provided outside the GPMC 0, 1, or 2 GPMC_FCLK cycles after start access time until RDCYCLETIME or WRCYCLETIME completion. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 587: Synchronous Single Read (Gpmcfclkdivider = 0)
Figure 5-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0) RDCYCLETIME RDACCESSTIME GPMC_FCLK CLKACTIVATIONTIME GPMC_CLK A[27:17] Valid Address WRDATAONADMUXBUS A[16:1]/D[15:0] Valid Address nBE1/nBE0 CSRDOFFTIME CSONTIME ADVRDOFFTIME ADVONTIME nADV OEOFFTIME OEONTIME WAIT SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 588: Synchronous Single Read (Gpmcfclkdivider = 1)
CS deassertion, plus time from RDACCESSTIME to CSRDOFFTIME. • Direction signal DIR: DIR goes from OUT to IN at the same time as OE assertion. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 589 After a read operation, if no other access (read or write) is pending, the data bus is driven with the previous read value. See Section 5.2.4.9.10. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 590: Synchronous Multiple (Burst) Read (Gpmcfclkdivider = 0)
RDACCESSTIME PAGEBURSTACCESSTIME CLKACTIVATIONTIME GPMC_FCLK GPMC_CLK A[27:17] Valid Address A[16:1]/D[15:0] Valid Address D1 D2 nBE1/nBE0 CSRDOFFTIME0 CSRDOFFTIME1 CSONTIME ADVRDOFFTIME ADVONTIME nADV OEOFFTIME OEONTIME WAIT General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 591: Synchronous Multiple (Burst) Read (Gpmcfclkdivider = 1)
Burst wraparound is enabled through the GPMC_CONFIG1_i[31] WRAPBURST bit and allows a 4-, 8-, or 16-Word16 linear burst access to wrap within its burst-length boundary through GPMC_CONFIG1_i[24-23] ATTACHEDDEVICEPAGELENGTH. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 592: Synchronous Single Write On An Address/Data-Multiplexed Device
When the GPMC generates a write access to an address/data-multiplexed device, it drives the data bus (with address bits A[16:1]) until [19:16] WRDATAONADMUXBUS time. First data of the burst is driven on the address/data bus at WRDATAONADMUXBUS time. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 593: Synchronous Multiple Write (Burst Write) In Address/Data-Multiplexed Mode
ADVONTIME nADV WEOFFTIME WEONTIME WAIT Figure 5-23 shows the same synchronous burst write access when the chip-select is configured in address/address/data-multiplexed (AAD-multiplexed) mode. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 594: Synchronous Multiple Write (Burst Write) In Address/Address/Data-Multiplexed Mode
Address valid signal ADV – ADV assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field. – ADV deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME field. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 595 Asynchronous single write operation on a nonmultiplexed device • Asynchronous multiple (page mode) read operation on a nonmultiplexed device • Synchronous operations on a nonmultiplexed device SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 596: Asynchronous Single Read On An Address/Data-Nonmultiplexed Device
GPMC_CONFIG1_5[4-0] RDCYCLETIME parameter. CS, ADV, OE and DIR signals are controlled in the same way as address/data multiplexed accesses, Section 5.2.4.10.1.1.2. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 597: Asynchronous Single Write On An Address/Data-Nonmultiplexed Device
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus D[15:0]. CS, ADV, WE and DIR signals are controlled in the same way as address/data multiplexed accesses, Section 5.2.4.10.1.1.3. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 598: Asynchronous Multiple (Page Mode) Read
Total access time RDCYCLETIME corresponds to RDACCESSTIME plus the address hold time starting from the CS deassertion. • The read cycle time is defined in the GPMC_CONFIG5_i[4-0] RDCYCLETIME field. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 599 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 600 NAND-specific multiphase access. In that sense, GPMC NAND support, as opposed to random memory-map device support, is data-stream-oriented (byte or 16-bit word). General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 601: Chip-Select Configuration For Nand Interfacing
NAND device in stream mode MUXADDDATA GPMC_CONFIG1_i 0b00 Nonmultiplexed mode TIMEPARAGRANULARITY GPMC_CONFIG1_i Timing achieved with best GPMC clock granularity GPMCFCLKDIVIDER GPMC_CONFIG1_i Don't care Asynchronous mode SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 602 16-bit word write access, the MSByte of the 16-bit word value must be set according to the NAND device requirement (usually 0). Either 16-bit word location or any one of the four byte locations of the registers is valid General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 603: Nand Command Latch Cycle
NAND Flash memories do not use byte enable signals at all. Figure 5-27. NAND Command Latch Cycle WRCYCLETIME CSWROFFTIME CSONTIME = 0 nBE0/CLE WEOFFTIME WEONTIME = 0 nADV/ALE D[15:0] Command SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 604: Nand Address Latch Cycle
Figure 5-28. NAND Address Latch Cycle WRCYCLETIME CSWROFFTIME = WRCYCLETIME CSONTIME = 0 nBE0/CLE WEOFFTIME WEONTIME = 0 ADVWROFFTIME = WRCYCLETIME ADVONTIME = 0 nADV/ALE D[15:0] Address General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 605: Nand Data Read Cycle
WE is controlled by the WEONTIME and WEOFFTIME timing parameters. • ALE, CLE, and RE (OE) are maintained inactive. Figure 5-30 shows the NAND data write cycle. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 606: Nand Data Write Cycle
16-bit word accesses to the NAND memory device. 16-bit word access is ordered according to little-endian organization. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 607 Depending on whether the GPMC_CONFIG WAITxPINPOLARITY bits (x = 0 or 1) is active low or active high, the wait-to-no-wait transition is a low-to-high external WAIT signal transition or a high-to-low external WAIT signal transition, respectively. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 608 It is the software responsibility to make sure only relevant data are passed to the NAND flash memory while the ECC computation engine is active. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 609 The ECC accumulator and ECC result register must not be changed or cleared while an ECC computation is in progress. Table 5-12 describes the ECC enable settings. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 610: Hamming Code Accumulation Algorithm (1 Of 2)
Row 255 Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit5 bit3 bit1 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 611: Hamming Code Accumulation Algorithm (2 Of 2)
P16o P16o Row 255 Row 255 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 612: Ecc Computation For A 512-Byte Data Stream (Read Or Write)
(LSB) of the 16-bit wide data is ordered first in the byte stream used for 8-bit based ECC computation. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 613: Word16 Ecc Computation
P16o P16o SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 614 ECC may or may not be protected by the same ECC scheme, by extending the BCH message beyond 512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of space to cover some spares bytes). General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 615: Flattened Bch Codeword Mapping (512 Bytes + 104 Bits)
Table 5-14. Aligned Message Byte Mapping in 8-bit NAND Byte Offset 8-Bit Word (msb) Byte 511 (1FFh) Byte 510 (1FEh) ⋮ ⋮ 1FFh Byte 0 (0) (LSB) SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 616: Aligned Message Byte Mapping In 16-Bit Nand
S/2 - 4 Nibble 5 Nibble 4 Nibble 7 Nibble 6 S/2 - 2 Nibble 1 Nibble 0 (LSB) Nibble 3 Nibble 2 616 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 617: Misaligned Nibble Mapping Of Message In 16-Bit Nand (1 Unused Nibble)
(concatenated message and remainder) once an error as been detected. The creation of this codeword should be made as straightforward as possible. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 618: Manual Mode Sequence And Mapping
Figure 5-37. Manual Mode Sequence and Mapping Manual mode to ECC divider unused Protected data Unused data Mode Size 0 Size 1 Rd/Wr/ bch_blk_ptr inactive size 0 size1 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 619 Repeat with buffer 0 to S-1 – size1 nibbles spare, processing ON Checksum: Spare area size (nibbles) = size0 + (S - size1) SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 620 – 1 nibble padding spare, processing OFF – size1 nibbles spare, processing ON Checksum: Spare area size (nibbles) = size0 + (S - (1+size1)) General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 621 Repeat S times (no buffer used) – size1 nibbles spare, processing OFF Checksum: Spare area size (nibbles) = S - (size0 + size1) SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 622 – sector 0 codeword: (512) + P + E – other sectors: (512) + E • Unprotected spares (Figure 5-38: see M4-M7-M8-M11-M12): – all codewords (512) + E General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 623: Nand Page Mapping And Ecc: Per-Sector Schemes
Data1 Unprot0 Ecc0 Unprot1 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write inactive size0 size0 Read inactive inactive size0 size1 size0 size1 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 624: Nand Page Mapping And Ecc: Pooled Spare Schemes
Data0 Data1 Unprotected (pooled) Ecc0 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write inactive +1+E size1 size1 Read inactive size0 size1 size1 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 625: Nand Page Mapping And Ecc: Per-Sector Schemes, With Separate Ecc
Data0 Data1 Unprot0 Unprot1 Ecc0 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write U+1+E inactive size1 size1 Read inactive size0 size1 size1 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 626: Prefetch And Write-Posting Engine
(the address bus is not changed from its current value). Selecting a different chip-select configuration can produce undefined behavior. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 627 In write-posting mode, when the FIFOPOINTER equals 0, that is, the FIFO is full, a host write overwrites the last FIFO byte location. There is no underflow or overflow error reporting in the GPMC. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 628: Prefetch Mode Configuration
Section 5.2.4.12.4.6 CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG1 Number of clock cycle removed to timing parameters ENABLEENGINE GPMC_PREFETCH_CONFIG1 Engine enabled STARTENGINE GPMC_PREFETCH_CONFIG1 Starts the prefetch engine 628 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 629 (the STARTENGINE bit is set to 1). The associated DMA channel must always be enabled by the MPU after setting the STARTENGINE bit so that the out-of-date active DMA request does not trigger spurious DMA transfers. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 630: Write-Posting Mode Configuration
Engine starts the access to chip-select as soon as STARTENGINE is set. ENABLEOPTIMIZEDACCESS GPMC_PREFETCH_CONFIG1 Section 5.2.4.12.4.6 CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG ENABLEENGINE GPMC_PREFETCH_CONFIG1 Engine enabled STARTENGINE GPMC_PREFETCH_CONTROL Starts the prefetch engine General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 631 In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte enables. Any byte stored in the FIFO is written into the memory device. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 632: Nand Read Cycle Optimization Timing Description
OEOFFTIME − x clk cycles nOE/nRE nADV/ALE D[15:0] Data 0 Data 1 WAIT x is the programmed value in the GPMC_PREFETCH_CONFIG1[30:28] CYCLEOPTIMIZATION field General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 633 Table 5-24 Table 5-25 list each step in the model. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 634: Programming Model Top-Level Diagram
9. Read operations (asynchronous) 10. ECC engine * 11. Prefetch and write posting engine * 12. Wait pin configuration * 13. Enable chip-select * Optional General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 635: Gpmc Configuration In Nor Mode
GPMC. Table 5-26. Reset GPMC Sub-process Name Register / Bitfield Value Start a software reset GPMC_SYSCONFIG[1] SOFTRESET Wait until GPMC_SYSSTATUS[0] RESETDONE SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 636: Nor Memory Type
GPMC_CONFIG1_i[17-16] WAITPINSELECT Table 5-31. Enable Chip-Select Sub-process Name Register / Bitfield Value When all parameters are configured, enable the chip-select GPMC_CONFIG7_i[6] CSVALID 636 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 637: Nand Memory Type
GPMC_ECC_SIZE_CONFIG[13-12] ECCBCHTSEL Set an error correction capability and and GPMC_ECC_SIZE_CONFIG[6-4] Select a number of sectors to process ECCTOPSECTOR Enable the ECC computation GPMC_ECC_SIZE_CONFIG[0] ECCENABLE SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 638: Wait Pin Configuration
WAITPINSELECTOR Table 5-38. Enable Chip-Select Sub-process Name Register / Bitfield Value When all parameters are configured, enable the chip-select GPMC_CONFIG7_i[6] CSVALID General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 639: Mode Parameters Check List Table
GPMC_CONFIG1_i WRITETYPE Table 5-40. Access Type Parameters Check List Table Access Type Register Bit Field Name Non-Mux Address/Data Mux AAD Mux GPMC_CONFIG1_i MUXADDDATA SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 640: Nor Interfacing Timing Parameters Diagram
Synchronous write write operation operation Asynchronous Synchronous read read Type of access? No read access Synch ronous Asynch ronous read read operation operation General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 641: Timing Parameters
12-8 OEOFFTIME GPMC_CONFIG4_i OEEXTRADELAY GPMC_CONFIG4_i OEONTIME GPMC_CONFIG5_i 27-24 PAGEBURSTACCESSTIME GPMC_CONFIG5_i 20-16 RDACCESSTIME GPMC_CONFIG5_i 12-8 WRCYCLETIME GPMC_CONFIG5_i RDCYCLETIME GPMC_CONFIG6_i 28-24 WRACCESSTIME GPMC_CONFIG6_i 19-16 WRDATAONADMUXBUS SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 642 (Burst) multiplexed multiplexed Access Access Access Access multiplexed access Access Access GPMC_CONFIG6_i 11-8 CYCLE2CYCLEDELAY GPMC_CONFIG6_i CYCLE2CYCLESAMECSEN GPMC_CONFIG6_i CYCLE2CYCLEDIFFCSEN GPMC_CONFIG6_i BUSTURNAROUND GPMC_CONFIG7_i CSVALID 642 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 643: Nand Formulas Description Table
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK period J = ((AccessTime - OEOffTime) * (TimeParaGranularity + 1) - 0.5 * OEExtraDelay)) * GPMC_FCLK period SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 644: Nand Command Latch Cycle Timing Simplified Example
Delay time - GPMC_CLK rising edge to GPMC_BE0_CLE/GPMC_BE1 transition Pulse duration - GPMC_ADV_ALE low Delay time - GPMC_WAIT invalid to first data latching GPMC_CLK edge 644 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 645 F = 0.5 * CSEXTRADELAY * GPMC_FCLK period, when (CSRDOFFTIME - CLKACTIVATIONTIME) is a multiple of 3 F = (1 + 0.5 * CSEXTRADELAY) * GPMC_FCLK period, when (CSRDOFFTIME - SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 646 G = 0.5 * ADVEXTRADELAY * GPMC_FCLK period • Case where GPMCFCLKDIVIDER = 0x1 G = 0.5 * ADVEXTRADELAY * GPMC_FCLK period, when (CLKACTIVATIONTIME and General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 647 CLKACTIVATIONTIME - 1) is a multiple of 3 I = (2 + 0.5 * WEEXTRADELAY) * GPMC_FCLK period, when (WEONTIME - CLKACTIVATIONTIME - 2) is a multiple of 3 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 648: Synchronous Nor Single Read Simplified Example
NOR single read simplified example where formulas are associated with signal waves. Figure 5-45. Synchronous NOR Single Read Simplified Example GPMC_FCLK GPMC_CLK Valid address nBE1/nBE0 nADV General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 649: Asynchronous Nor Formulas Description Table
F = ((WEOFFTIME - CSONTIME) * (TIMEPARAGRANULARITY + 1) + 0.5 * (WEEXTRADELAY - CSEXTRADELAY)) * GPMC_FCLK period G = CYCLE2CYCLEDELAY * GPMC_FCLK period SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 650: Asynchronous Nor Single Write Simplified Example
Write multiple access is not supported in asynchronous mode. If WRITEMULTIPLE is enabled with WRITETYPE as asynchronous, the GPMC processes single asynchronous accesses. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 651 Output enable (read access only) GPMC_WE Write enable (write access only) GPMC_WAIT[1:0] Ready signal from memory device. Indicates when valid burst data is ready to be read SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 652: Gpmc Connection To An External Nor Flash Memory
The following sections demonstrate how to calculate GPMC parameters for three access types: • Synchronous burst read • Asynchronous read • Asynchronous single write General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 653: Useful Timing Parameters On The Memory Side
Read cycle time (GPMC side): Read Access time + access completion • Write cycle time for burst access: Not supported for NOR flash memory SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 654: Synchronous Burst Read Access (Timing Parameters In Clock Cycles)
(access time on memory side) AdvRdOffTime = 2 nADV CsReadOffTime = RdCycleTime OeOffTime = RdCycleTime OeOnTime = 3 A/D bus Valid Address General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 655: Ac Characteristics For Asynchronous Read Access
To complete the access, OE/CS signals are driven to high-impedance. AccessTime + 1 + tOEZ is the read cycle time. • Addresses can now be relatched and a new read cycle begun. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 656: Asynchronous Single Read Access (Timing Parameters In Clock Cycles)
AdvRdOffTime = 1 nADV tOEZ OeOffTime = 10 OeOnTime = 3 Memory-side access time Data Hold time A/D bus Valid Address DATA Valid Address General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 657: Ac Characteristics For Asynchronous Single Write (Memory Side)
For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion = WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CS de-assertion). SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 658: Asynchronous Single Write Access (Timing Parameters In Clock Cycles)
WeOnTime = 2 (at least 1) At least > 20 ns (tWPH) At least > 25 ns (tWP) ADDRESS ADDRESS A/D bus DATA DATA General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 659: Supported Memory Interfaces
IO15 GPMC_D[14] D14 or A15 D14 or A15 D14 or A15 IO14 GPMC_D[13] D13 or A14 D13 or A14 D13 or A14 IO13 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 660 WP (Write Protect) WP (write protect) WP (write protect) GPMC_WAIT0 WAIT0 WAIT0 WAIT0 R/B0 (ready/busy) R/B0 (ready/busy) GPMC_WAIT1 WAIT1 WAIT1 WAIT1 R/B1 (ready/busy) R/B1 (ready/busy) General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 661: Nand Interface Bus Operations Summary
Asserted Output Read (synchronous) Running Driven Output Read (burst suspend) Halted Active Output Write Asserted Input Output disable Asserted High-Z Standby High-Z High-Z SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 662 Data path to external memory or device: 8- and 16-bit wide • Burst and page access: burst of 4-8-16 Word16 • Supports bus keeping • Supports bus turn around General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 663: Gpmc Registers
308h + (10h × i) GPMC_BCH_RESULT6_i Section 5.5.36 2D0h GPMC_BCH_SWDATA Section 5.5.33 i = 0 to 7 for GPMC j = 0 to 8 for GPMC SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 664: 5.5.1 Gpmc_Revision
The module is reset AUTOIDLE Internal OCP clock gating strategy Interface clock is free-running Automatic Interface clock gating strategy is applied, based on the Interconnect activity General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 665: 5.5.3 Gpmc_Sysstatus
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-58. GPMC_SYSSTATUS Field Descriptions Field Value Description 31-1 Reserved Reserved RESETDONE Internal reset monitoring Internal module reset in on-going Reset completed SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 666: 5.5.4 Gpmc_Irqstatus
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode and at least FIFOTHRESHOLD bytes free places are available in write-posting mode. FIFOEVENTSTATUS bit is reset General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 667: 5.5.5 Gpmc_Irqenable
TerminalCountEvent interrupt is masked TerminalCountEvent interrupt is not masked FIFOEVENTENABLE Enables the FIFOEvent interrupt FIFOEvent interrupt is masked FIFOEvent interrupt is not masked SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 668: 5.5.6 Gpmc_Timeout_Control
Reserved 30-0 ILLEGALADD 0-7FFF FFFFh Address of illegal access: A30 (0 for memory region, 1 for GPMC register region) and A29-A0 (1GByte maximum) General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 669: 5.5.8 Gpmc_Err_Type
Error validity status - Must be explicitly cleared with a write 1 transaction All error fields no longer valid Error detected and logged in the other error fields SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 670: 5.5.9 Gpmc_Config
Limited Address device support NANDFORCEPOSTEDWRITE Enables the Force Posted Write feature to NAND Cmd/Add/Data location Disables Force Posted Write Enables Force Posted Write General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 671: 5.5.10 Gpmc_Status
WAIT0 asserted (inactive state) WAIT0 de-asserted Reserved Reserved EMPTYWRITEBUFFERSTATUS Stores the empty status of the write buffer Write Buffer is not empty Write Buffer is empty SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 672: 5.5.11 Gpmc_Config1_I
Reserved 24-23 ATTACHEDDEVICEPAGELENGTH Specifies the attached device page (burst) length (1 Word = Interface size) 4 Words 8 Words 16 Words Reserved General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 673 Signals timing latencies scalar factor (Rd/WRCycleTime, AccessTime, PageBurstAccessTime, CSOnTime, CSRd/WrOffTime, ADVOnTime, ADVRd/WrOffTime, OEOnTime, OEOffTime, WEOnTime, WEOffTime, Cycle2CycleDelay, BusTurnAround, TimeOutStartValue) ×1 latencies ×2 latencies Reserved Reserved SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 674 Divides the GPMC.FCLK clock GPMC_CLK frequency = GPMC_FCLK frequency GPMC_CLK frequency = GPMC_FCLK frequency/2 GPMC_CLK frequency = GPMC_FCLK frequency/3 GPMC_CLK frequency = GPMC_FCLK frequency/4 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 675: 5.5.12 Gpmc_Config2_I
CS i Timing control signal is delayed of half GPMC_FCLK clock cycle Reserved Reserved CSONTIME CS# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 676: 5.5.13 Gpmc_Config3_I
ADV# Add Extra Half GPMC.FCLK cycle ADV Timing control signal is not delayed ADV Timing control signal is delayed of half GPMC_FCLK clock cycle General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 677 ⋮ 7 GPMC_FCLK cycles ADVONTIME ADV# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 678: 5.5.14 Gpmc_Config4_I
OE# Add Extra Half GPMC.FCLK cycle OE Timing control signal is not delayed OE Timing control signal is delayed of half GPMC_FCLK clock cycle General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 679 ⋮ 7 GPMC_FCLK cycles OEONTIME OE# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 680: 5.5.15 Gpmc_Config5_I
⋮ ⋮ 31 GPMC_FCLK cycles Reserved Reserved RDCYCLETIME Total read cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 31 GPMC_FCLK cycles General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 681: 5.5.16 Gpmc_Config6_I
(read to write) or to a different chip-select (read to read and read to write) 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 682: 5.5.17 Gpmc_Config7_I
CSi base address where i = 0 to 3 (16 Mbytes minimum granularity). Bits [5-0] corresponds to A29, A28, A27, A26, A25, and A24. General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 683: 5.5.18 Gpmc_Nand_Command_I
0-FFFF FFFFh Reading data from the GPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access. SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 684: 5.5.21 Gpmc_Prefetch_Config1
The two next accesses are granted to the PFPW engine ⋮ ⋮ The 16 next accesses are granted to the PFPW engine Reserved Reserved General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 685 DMA request synchronization is enabled. A DMA request protocol is used. Reserved Reserved ACCESSMODE Selects pre-fetch read or write posting accesses Prefetch read mode Write-posting mode SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 686: 5.5.22 Gpmc_Prefetch_Config2
Stops the engine Engine is running Resets the FIFO pointer to 0 in prefetch mode and 40h in postwrite mode and starts the engine General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 687: 5.5.24 Gpmc_Prefetch_Status
1 byte remaining to be read or to be writte ⋮ ⋮ 2000h 8 Kbytes remaining to be read or to be written SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 688: 5.5.25 Gpmc_Ecc_Config
Chip-select 0 Chip-select 1 Chip-select 2 Chip-select 3 Chip-select 4 Chip-select 5 6h-7h Reserved ECCENABLE Enables the ECC feature ECC disabled ECC enabled General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 689: 5.5.26 Gpmc_Ecc_Control
ECC result register 5 selected ECC result register 6 selected ECC result register 7 selected ECC result register 8 selected ECC result register 9 selected SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 690: 5.5.27 Gpmc_Ecc_Size_Config
Selects ECC size for ECC 6 result register ECCSIZE0 selected ECCSIZE1 selected ECC5RESULTSIZE Selects ECC size for ECC 5 result register ECCSIZE0 selected ECCSIZE1 selected General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 691 Selects ECC size for ECC 2 result register ECCSIZE0 selected ECCSIZE1 selected ECC1RESULTSIZE Selects ECC size for ECC 1 result register ECCSIZE0 selected ECCSIZE1 selected SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 692: 5.5.28 Gpmc_Eccj_Result
Even Row Parity bit 16 Even Row Parity bit 8 Even Column Parity bit 4 Even Column Parity bit 2 Even Column Parity bit 1 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 693: 5.5.29 Gpmc_Bch_Result0_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-86. GPMC_BCH_RESULT2_i Field Descriptions Field Value Description 31-0 BCH_RESULT2_i 0-FFFF FFFFh BCH ECC result, bits 64 to 95 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 694: 5.5.32 Gpmc_Bch_Result3_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-89. GPMC_BCH_RESULT4_i Field Descriptions Field Value Description 31-0 BCH_RESULT4_i 0-FFFF FFFFh BCH ECC result, bits 128 to 159 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 695: 5.5.35 Gpmc_Bch_Result5_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-91. GPMC_BCH_RESULT6_i Field Descriptions Field Value Description 31-0 BCH_RESULT6_i 0-FFFF FFFFh BCH ECC result, bits 192 to 207 SPRUGX9 – 15 April 2011 General-Purpose Memory Controller (GPMC) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 696 General-Purpose Memory Controller (GPMC) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 697 SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) This chapter describes the high-definition multimedia interface (HDMI) module......................... Topic Page ....................Introduction ....................Architecture ....................Registers SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 698: Hdmi Overview
Video formats: 24-bit RGB • Uncompressed multichannel (up to eight channels) audio (L-PCM) support • Master inter-intergrated circuit (I2C) interface for display data channel (DDC) connection High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 699: Hdmi Block Diagram
HDMI module, according to the CEA-861-D standard. Table 6-2 lists the video timings supported by the HDMI module, according to the VESA DMT standard. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 700: Hdmi Video Timings (Cea-861-D)
1920 x 1080p 1280 x 768p 1280 x 800p 60 Hz (reduced blanking) 1400 x 1050p 1440 x 900p 1680 x 1050p 700 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 701: Hdmi Environment
HDMI_TXPHY module after TDMS encoding, if there is no HDCP encryption enabled. • Audio data path: – Level 3 (L3) interconnect – HDMI module – HDMI complex I/O (HDMI_TXPHY) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 702: Cec Clock Generation
OCP_TIME_OUT_INTR interrupt, see Section 6.2.6. The time-out capability can be disabled by writing 1 to the HDMI_WP_CLK[16] OCP_TIME_OUT_DIS bit. By default, this option is enabled. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 703: Hdmi I/O Signal Description
This has the same effect as a hardware reset. The HDMI module can be reset by setting the HDMI_WP_SYSCONFIG[0] SOFTRESET bit to 1. Software can monitor this bit to wait for the reset to complete. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 704: Hdmi Integration
Sleep (Idle) and Wake-Up Management, in Power, Reset, and Clock Management. Table 6-5. Integration Attributes Module Instance Attributes Power Domain — Interconnect HDMI Active Domain —L3 for Data; L4 for Configuration High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 705: Clocks And Resets
Table 6-8. Local Power-Management Features Feature Registers Description Slave idle modes HDMI_WP_SYSCONFIG[3:2] IDLEMODE bit field Force-idle, no-idle, smart-idle, and smart-idle wakeup-capable modes are available. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 706: Hdmi Interrupt Events
VESA DMT video timings support at 60 Hz (reduced blanking included) – 10 bits per color component for 1080p/60fps and 1080p/50fps – 12 bits per color component High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 707: Video Port Signals
HDMI_VIDEO_DATA[22] VPSS_DATA[17] HDMI_VIDEO_DATA[21] VPSS_DATA[16] HDMI_VIDEO_DATA[20] VPSS_DATA[15] HDMI_VIDEO_DATA[19] VPSS_DATA[14] HDMI_VIDEO_DATA[18] VPSS_DATA[13] HDMI_VIDEO_DATA[17] VPSS_DATA[12] HDMI_VIDEO_DATA[16] VPSS_DATA[11] HDMI_VIDEO_DATA[15] VPSS_DATA[10] HDMI_VIDEO_DATA[14] HDMI_VIDEO_DATA[13] HDMI_VIDEO_DATA[12] VPSS_DATA[9] HDMI_VIDEO_DATA[11] VPSS_DATA[8] HDMI_VIDEO_DATA[10] SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 708 HDMI Core 8-bit registers of the 32-bit access, starting with the least-significant bit (LSB) to the MSB. Figure 6-5 is an overview of the audio interface to the HDMI core. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 709: Hdmi Audio Interface Overview
32-bit data (in case of two samples per word) or 4 × 32-bit data (IEC or one sample per word). The interconnect latency must be considered. The number of samples is controlled through the HDMI_WP_AUDIO_CFG[1] SAMPLE_NBR bit. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 710: Pcm, 16-Bit Format
Left - Channel 1 Right - Channel 4 Left - Channel 3 16 bits, 8 channels Right - Channel 2 Left - Channel 1 710 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 711: Pcm, 24-Bit Format
6-14. The CEA code is used to program the Packet Byte 4 of the Audio Info FRAME register inside the HDMI core (for more information, see the HDMI standard v1.3). Table 6-14. Speaker Mapping Versus Channel CEA Code SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 712 Preliminary Architecture www.ti.com Table 6-14. Speaker Mapping Versus Channel (continued) CEA Code 712 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 713: Audio Data Stuffing Behavior
HDMI core module, the function must be set to 3h in the HDMI_WP_AUDIO_CFG[26:24] STEREO_CHANNEL_ENABLE bit field. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 714: Audio Data Stuffing Behavior With Only Three Stereo Channels Active
Left - Channel 3 Preamble VUCP Right - Channel 4 Preamble VUCP Left - Channel 5 Preamble VUCP Right - Channel 6 Preamble 714 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 715: 6.2.9.2.4.2 L-Pcm 16-Bit Format Adaptation
DATA 1 RIGHT DATA 1 LEFT DATA 2 LEFT 0x00 0x00 DATA 2 RIGHT 0x00 0x00 DATA 2 RIGHT DATA 2 LEFT Adaptation SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 716 The serialized data on differential output lines DX/DY has the order LSB first and MSB last. The TMDS clock on the clock lane has a falling edge at the start of the 10-bit serial data word on the line. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 717: Transmitter Video Data Processing Path
Range Clipping 14 to Packetizer TMDS YCbCr Decimation Expansion Compression 8/10/12 Mask Bypass Bypass Bypass Bypass Bypass Bypass CSC Expansion Compression Clipping Dither SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 718: Ip Revision Identifier Register (Hdmi_Wp_Revision)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-18. IP Revision Identifier Register (HDMI_WP_REVISION) Field Description 31-0 Revision IP Revision High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 719: Clock Management Configuration Register (Hdmi_Wp_Sysconfig)
(IRQ- or DMA-request-related) wakeup events when in idle state. Reserved Reserved SOFTRESET Software reset. (Optional) Software reset done, no pending action No action Software reset ongoing Initiate software reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 720: Raw Interrupt Status Register (Hdmi_Wp_Irqstatus_Raw)
Set event Reserved Reserved OCP_TIME_OUT_INTR Settable raw status for OCP timeout interrupt No event pending No action IRQ event pending Set event Reserved Reserved High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 721 Value Description CORE_INTR Settable raw status for HDMI Core interrupt Software reset done, no pending action No action Software reset ongoing Set event SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 722: Interrupt Status Register (Hdmi_Wp_Irqstatus)
Clear pending event, if any Set event Reserved Reserved CORE_INTR Software reset done, no pending action No action Clear pending event, if any Set event High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 723: Interrupt Enable Register (Hdmi_Wp_Irqenable_Set)
Enable interrupt Reserved Reserved ENABLE_SET_OCP_TIME_OUT_INTR Enable for interrupt events for OCP timeout interrupt Interrupt disabled No action Interrupt enabled Enable interrupt Reserved Reserved SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 724 Table 6-22. Interrupt Enable Register (HDMI_WP_IRQENABLE_SET) Field Descriptions (continued) Field Value Description ENABLE_SET_CORE_INTR Enable for audio interrupt events for core interrupt Interrupt disabled No action Interrupt enabled Enable interrupt High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 725: Interrupt Disable Register (Hdmi_Wp_Irqenable_Clear)
ENABLE_CLEAR_AUDIO_FIFO_ Interrupt disabled UNDERFLOW_INTR No action Interrupt enabled Enable interrupt Reserved Reserved ENABLE_CLEAR_OCP_TIME_OUT_INTR Interrupt disabled No action Interrupt enabled Enable interrupt Reserved Reserved SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 726 Registers www.ti.com Table 6-23. Interrupt Disable Register (HDMI_WP_IRQENABLE_CLEAR) Field Descriptions (continued) Field Value Description ENABLE_CLEAR_CORE_INTR Interrupt disabled No action Interrupt enabled Enable interrupt High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 727: Glitch Filter Register (Hdmi_Wp_Debounce)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-25. Configuration of HDMI Wrapper Video Register (HDMI_WP_VIDEO_CFG) Field Descriptions Field Value Description 31-11 Reserved Reserved SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 728: Configuration Of Hdmi Wrapper Video Register (Hdmi_Wp_Video_Cfg) Field Descriptions
Enables to invert or not the HSYNC signal provided to the HDMI core HSYNC is unchanged HSYNC is inverted Reserved Reserved MODE Always program to 0 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 729: Configuration Of Clocks Register (Hdmi_Wp_Clk)
CEC_DDC clock (48MHz). If 48 MHz is provided, the division by 24 is required (18h) to get the expected CEC clock speed (2 MHz) The valid values are from 0 to 63. Gated Free-running SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 730: Audio Configuration In Fifo Register (Hdmi_Wp_Audio_Cfg)
This field indicates the number of sample per word (32 bits) (not applicable if IEC format) 1 sample per word, 32 bit 2 samples per word, 32 bits (only compatible with sample on 16 bits) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 731 Audio sample size, 16 bits or 24 bits (not applicable if IEC format) Sample is on 16 bits Sample is on 24 bits SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 732: Audio Configuration Of Dma Register (Hdmi_Wp_Audio_Cfg2)
NUMBER_OF_SAMPLE Shows the number of valid sample (16 or 24 bits) in the FIFO (depends of the fifo format setting) 15-10 Reserved Reserved High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 733: Tx Data Of Fifo Register (Hdmi_Wp_Audio_Data)
Table 6-30. TX Data of FIFO Register (HDMI_WP_AUDIO_DATA) Field Descriptions Field Description 31-0 FIFO_DATA Audio TX DATA. Can be accessed in 32-bit mode only. Read returns 0. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 734: Hdmi_Ip_Core_System Registers Summary
Video HSYNC Length Register 114h HWIDTH2 Video HSYNC Length Register 118h VBIT_TO_VSYNC Video Vbit to VSYNC Register 11Ch VWIDTH Video VSYNC Length Register 734 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 735 240h XVYCC2RGB_CTL xvYCC_2_RGB Control Register 244h Y2R_COEFF_LOW xvYCC_2_RGB Conversion Y_2_R Register 248h Y2R_COEFF_UP xvYCC_2_RGB Conversion Y_2_R Register 24Ch CR2R_COEFF_LOW xvYCC_2_RGB Conversion Cr_2_R Register SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 736: Vendor Id Register (Vnd_Idl)
Table 6-32. Vendor ID Register (VND_IDL) Field Descriptions Field Description 31-8 Reserved Reserved VND_IDL Vendor ID low byte. Provides unique vendor identification through I2C. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 737: Vendor Id Register (Vnd_Idh)
Device ID high byte. Provides unique vendor identification through I2C. 6.3.2.5 Device Revision Register (DEV_REV) The device revision register is shown in Figure 6-27 and desribed in Table 6-36. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 738: Device Revision Register (Dev_Rev)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-36. Device Revision Register (DEV_REV) Field Descriptions Field Description 31-8 Reserved Reserved DEV_REV Allows distinction between revisions of same device. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 739: Software Reset Register (Srst)
The current status of the VSYNC input pin. Refer to the INTR2 register for an interrupt tied to VSYNC active edge. VSYNC enable Fixed LOW Follow VSYNC input HSYNC enable Fixed LOW Follow HSYNC input SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 740 HIGH is normal operation. When LOW, interrupts are in power-down mode. Most other register values are not affected by assertion of the PD bit. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 741: System Status Register (Sys_Stat)
Reserved The states of these control bits are transmitted across the TMDS link during blanking times for DVI 1.0 mode only. Reserved Reserved SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 742: Data Control Register (Dctl)
When connected to 1 b0; enables firmware to take the decision whether to send unencrypted data or not. By connecting to 1 b1; HDMI Tx will be able to send ONLY encrypted data. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 743: Hdcp Control Register (Hdcp_Ctrl)
Encryption enabled. See description of HDCP_SEL bit-field in DCTL register. 6.3.2.12 HDCP BKSV Register (BKSV__0-BKSV__4) The HDCP BKSV register is shown in Figure 6-34 and described in Table 6-43. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 744: Hdcp Bksv Register (Bksv
Write : Written with the HDCP receiver key selection vector register value. Writing 5th BKSV byte triggers the authentication logic in the HDMI Transmitter. Write this byte last. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 745: Hdcp An Register (An
R1i register. The value of this register should be read and compared with the HDMI Receiver s Ri value. 6.3.2.16 HDCP Ri2 Register (RI2) The HDCP Ri2 register is shown in Figure 6-38 and described in Table 6-47. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 746: Hdcp Ri2 Register (Ri2)
RI_128_COMP Limit counter for Ri comparison. When the frame counter (I_CNT) reaches the index set in this register an RI_128 interrupt is generated. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 747: Hdcp I Counter Register (I_Cnt)
Figure 6-42. Ri Command Register (RI_CMD) Reserved R-0h Reserved BCAP_EN RI_EN R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 748: Ri Line Start Register (Ri_Start)
Indicates at what line within frame 127 or 0 to start the Ri Check. Note: The value for this register bit represents the power of 2; 2 LSB is 0. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 749: Ri From Rx Registers (Low) (Ri_Rx_L)
Reserved R-0h Reserved R-0h RI_DBG_ RI_DBG_ Reserved TRASH HOLD R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 750: Video De Delay Register (De_Dly)
(HSYNC width) + (horizontal back porch) + (horizontal left border), and is used only for DE generation. Note: This 12-bit value includes four bits from register DE_CTRL. The valid range is 1-4095. 0 is invalid. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 751: Video De Control Register (De_Ctrl)
(VSYNC width) + (vertical back porch) + (vertical top border). The valid range is 1-127. 0 is invalid. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 752: Video De Count Register (De_Cntl)
The valid range is 1-4095. 0 is invalid. The bit-field defines DE_CNT[7:0]. The value DE_CNT[11:8] is defined in DE_CNTH register. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 753: Video De Count Register (De_Cnth)
The valid range is 1-2047. 0 is invalid. The bit-field defines DE_LIN[10:8]. The value DE_LIN[7:0] is defined in DE_LINL register. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 754: Video H Resolution Register (Hres_L)
Measures the time between two HSYNC active edges. The unit of measure is pixels. The bit-field defines H_RES[7:0]. The value H_RES[12:8] is defined in H_RESH register. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 755: Video H Resolution Register (Hres_H)
Measures the time between two VSYNC active edges. The unit of measure is lines. The bit-field defines VRES[10:8]. The value VRES[7:0] is defined in VRES_L register. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 756: Video Interlace Adjustment Register (Iadjust)
2 of an interlace frame If F2VADJ and this bit is set; VBIT_TO_VSYNC is incremented by one during field 2 of an interlace frame High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 757: Video Sync Polarity Detection Register (Pol_Detect)
6.3.2.39 Video Hbit to HSYNC Register (HBIT_2HSYNC2) The video Hbit to HSYNC register is shown in Figure 6-61 and described in Table 6-70. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 758: Video Hbit To Hsync Register (Hbit_2Hsync2)
1 to 0) to the active edge of HSYNC. The unit of measure is pixels. HBIT_TO_HSYNC[9:0].The valid range is 1-1023. 0 is invalid. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 759: Video Field2 Hsync Offset Register (Fld2_Hs_Ofstl)
HWIDTH Sets the width of the HSYNC pulses. Set this register to the desired HSYNC pulse width. The unit of measure is pixels. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 760: Video Hsync Length Register (Hwidth2)
Sets the width of the HSYNC pulses. Set this register to the desired HSYNC pulse width. The unit of measure is pixels. The valid range is 1-1023. 0 is invalid. HWIDTH[9:0] High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 761: Video Vbit To Vsync Register (Vbit_To_Vsync)
IFPOL Reserved EXTN CSCSEL Reserved ICLK R-0h R-0h R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 762: Video Control Register (Vid_Ctrl) Field Descriptions
For example, if DEMUX = 1 and ICLK = 0b01, set the pixel replication field of AVI v2 data byte 5 to 0b11. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 763: Video Action Enable Register (Vid_Acen)
Enable RGB to YCbCr color-space converter Disabled Enabled RANGE_CMPS Enable range compress 0-255 to 16-234 Disabled Enabled DOWN_SMPL Enable down sampler 4:4:4 to 4:2:2 Disabled Enabled SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 764: Video Mode1 Register (Vid_Mode)
YcbCr to RGB color space conversion Disabled Enabled UPSMP Upsampling 4:2:2 to 4:4:4 Disabled Enabled DEMUX One- to two-data-channel demux Disabled Enabled SYNCEX Embedded sync extraction Disabled Enabled High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 765: Video Blanking Register (Vid_Blank1)
Defines the video blanking value for Channel 3 (Red). 6.3.2.52 Deep Color Header Register (DC_HEADER) The deep color header register is shown in Figure 6-74 and described in Table 6-83. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 766: Deep Color Header Register (Dc_Header)
Reserved Reserved DC_HEADER This is the least siginificant byte of the deep color header that sends the TMDS dynamic phase once per frame. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 767: Video Mode2 Register (Vid_Dither)
Disable the function Enable the function 6.3.2.54 RGB_2_xvYCC Control Register (RGB2XVYCC_CT) The RGB_2_xvYCC control register is shown in Figure 6-76 and described in Table 6-85. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 768: Rgb_2_Xvycc Control Register (Rgb2Xvycc_Ct)
Disable the function Enable the function XV_FUS xvYCC fullscale mode Disable the function Enable the function XV_EN xvYCC enable Disable the function Enable the function High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 769: Rgb_2_Xvycc Conversion R_2_Y Register (R2Y_Coeff_Low)
Reserved Reserved G2YCOEFF_L RGB to xvYCC conversion G to Y coefficient lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 770: Rgb_2_Xvycc Conversion G_2_Y Register (G2Y_Coeff_Up)
Reserved Reserved G2YCOEFF_H RGB to xvYCC conversion G to Y coefficient lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 771: Rgb_2_Xvycc Conversion B_2_Y Register (B2Y_Coeff_Low)
Reserved Reserved R2CBCOEFF_L RGB to xvYCC conversion R to Cb coefficient lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 772: Rgb_2_Xvycc Conversion R_2_Cb Register (R2Cb_Coeff_Up)
Reserved Reserved R2CBCOEFF_H RGB to xvYCC conversion R to Cb coefficient upper byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 773: Rgb_2_Xvycc Conversion G_2_Cb Register (G2Cb_Coeff_Low)
Reserved Reserved B2CBCOEFF_L RGB to xvYCC conversion B to Cb coefficient lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 774: Rgb_2_Xvycc Conversion B_2_Cb Register (B2Cb_Coeff_Up)
Reserved Reserved B2CBCOEFF_H RGB to xvYCC conversion B to Cb coefficient upper byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 775: Rgb_2_Xvycc Conversion R_2_Cr Register (R2Cr_Coeff_Low)
Reserved Reserved G2CRCOEFF_L RGB to xvYCC conversion G to Cr coefficient lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 776: Rgb_2_Xvycc Conversion G_2_Cr Register (G2Cr_Coeff_Up)
Reserved Reserved G2CRCOEFF_H RGB to xvYCC conversion G to Cr coefficient upper byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 777: Rgb_2_Xvycc Conversion B_2_Cr Register (B2Cr_Coeff_Low)
Table 6-104. RGB_2_xvYCC RGB Input Offset Register (RGB_OFFSET_LOW) Field Descriptions Field Description 31-8 Reserved Reserved RGB_OFFS_L Input RGB offset value lower byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 778: Rgb_2_Xvycc Rgb Input Offset Register (Rgb_Offset_Up)
Table 6-105. RGB_2_xvYCC RGB Input Offset Register (RGB_OFFSET_UP) Field Descriptions Field Description 31-8 Reserved Reserved RGB_OFFS_H Input RGB offset value upper byte (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 779: Rgb_2_Xvycc Conversion Y Output Offset Register (Y_Offset_Low)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-108. RGB_2_xvYCC Conversion CbCr Output Offset Register (CBCR_OFFSET_LOW) Field Descriptions Field Description 31-7 Reserved Reserved SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 780: Rgb_2_Xvycc Conversion Cbcr Output Offset Register (Cbcr_Offset_Up)
Field Description 31-7 Reserved Reserved CBCR_OFFS_H Output CbCr offset value upper 7 bits (override internal CSC value when program reg RGB_2_XVYCC.XV_CO_OV = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 781: Interrupt State Register (Intr_State)
RI_128_COMP is matched by the VSYNC (frame) counter in the HDMI transmitter. It should trigger the firmware to perform a link integrity check. Such a match occurs every 128 frames. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 782 HDMI link. Such a condition can occur from a transient change in the Fs or pixel clock rate. UNDER_RUN Audio FIFO underflow. Similar to OVER_RUN, this interrupt occurs when the audio FIFO empties. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 783: Interrupt Source Register (Intr2)
FULL EMPTY R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 784: Interrupt Source Register (Intr3) Field Descriptions
DDC FIFO is full. DDC_FIFO_EMPT DDC FIFO is empty. Reset value is 0, but can be set after reset since the fifo is empty. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 785: Interrupt Source Register (Intr4)
OVER_RUN UNDER_RUN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 786: Interrupt Unmask Register (Int_Unmask1) Field Descriptions
HDMI link. Such a condition can occur from a transient change in the Fs or pixel clock rate. UNDER_RUN Audio FIFO underflow. Similar to OVER_RUN. This interrupt occurs when the audio FIFO empties. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 787: Interrupt Unmask Register (Int_Unmask2)
FULL EMPTY R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 788: Interrupt Unmask Register (Int_Unmask3) Field Descriptions
DDC FIFO is full. DDC_FIFO_EMPT DDC FIFO is empty. Reset value is 0, but can be set after reset since the fifo is empty. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 789: Interrupt Unmask Register (Int_Unmask4)
R-0h Reserved R-0h Reserved SOFT_INTR OPEN_DRAIN POLARITY Reserved R-0h R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 790: Xvycc_2_Rgb Control Register (Xvycc2Rgb_Ctl)
This bit indicates the source is xvYCC when 1, YcbCr when 0. It can be configured by firmware. Under auto video configure (AVC) mode, this control comes from HDMI packet decoding. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 791: Xvycc_2_Rgb Conversion Y_2_R Register (Y2R_Coeff_Low)
Reserved Reserved CR2RCOEFF_L xvYCC to RGB conversion Cr to R coefficient lower byte (override internal CSC value when program reg XVYCC_2_RGB.SW_OVR = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 792: Xvycc_2_Rgb Conversion Cr_2_R Register (C2R2R_Coeff_Up)
Reserved Reserved CR2RCOEFF_H xvYCC to RGB conversion Cr to R coefficient upper byte (override internal CSC value when program reg XVYCC_2_RGB.SW_OVR = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 793: Xvycc_2_Rgb Conversion Cb_2_B Register (Cb2B_Coeff_Low)
Reserved Reserved CR2GCOEFF_L xvYCC to RGB conversion Cr to G coefficient lower byte (override internal CSC value when program reg XVYCC_2_RGB.SW_OVR = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 794: Xvycc_2_Rgb Conversion Cr_2_G Register (Cr2G_Coeff_Up)
Reserved Reserved CR2GCOEFF_H xvYCC to RGB conversion Cr to G coefficient upper byte (override internal CSC value when program reg XVYCC_2_RGB.SW_OVR = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 795: Xvycc_2_Rgb Conversion Cb_2_G Register (Cb2G_Coeff_Low)
Table 6-131. xvYCC_2_RGB Conversion Y Offset Register (YOFFSET1_LOW) Field Descriptions Field Description 31-8 Reserved Reserved YOFFS1_L xvYCC2RGB Y offset coefficient lower byte (override internal CSC value when program XVYCC2RGB_CTL.SW_OVR = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 796: Xvycc_2_Rgb Conversion Y Offset Register (Yoffset1_Up)
Table 6-132. xvYCC_2_RGB Conversion Y Offset Register (YOFFSET1_UP) Field Descriptions Field Description 31-4 Reserved Reserved YOFFS1_H xvYCC2RGB Y offset coefficient upper byte (override internal CSC value when program XVYCC2RGB_CTL.SW_OVR = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 797: Xvycc_2_Rgb Conversion Offset1 Register (Offset1_Low)
Table 6-135. xvYCC_2_RGB Conversion Offset1 Register (OFFSET1_UP) Field Descriptions Field Description 31-8 Reserved Reserved OFFS1_H xvYCC2RGB offset1 coefficient upper byte (override internal CSC value when program XVYCC2RGB_CTL.SW_OVR = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 798: Xvycc_2_Rgb Conversion Offset2 Register (Offset2_Low)
Offset for RGB channel before right shifting, which is subtractive if software override is on (override internal CSC value when program XVYCC2RGB_CTL.SW_OVR = 1) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 799: Xvycc_2_Rgb Conversion Offset2 Register (Offset2_Up)
Table 6-139. xvYCC_2_RGB Conversion DC Level Register (DCLEVEL_UP) Field Descriptions Field Description 31-6 Reserved Reserved DC_LEV_H xvYCC2RGB DC lelvel coefficient upper byte (override internal CSC value when program rXVYCC2RGB_CTL.SW_OVR = 1) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 800: Ddc I2C Manual Register (Ddc_Man)
Override port with MAN_SCL and MAN_SDA states Reserved Reserved MAN_SDA Manual SDA output MAN_SCL Manual SCL output Reserved Reserved IO_SCL DDC SCL input state IO_SDA DDC SDA input state High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 801: Ddc I2C Target Slave Address Register (Ddc_Addr)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-143. DDC I2C Target Offset Address Register (DDC_OFFSET) Field Descriptions Field Description 31-8 Reserved Reserved DDC_OFFSET DDC offset address SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 802: Ddc I2C Data Count Register (Ddc_Count1)
DDC bus. For example, if the HDCP KSV FIFO length is 635 bytes (127 devices x 5 bytes/KSV), the DDC_COUNT must be 27Bh. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 803: Ddc I2C Data Count Register (Ddc_Count2)
1 = DDC FIFO full FIFO_EMP 1 = DDC FIFO empty FRD_USE 1 = DDC FIFO read in use FWT_USE 1 = DDC FIFO write in use SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 804: Ddc I2C Command Register (Ddc_Cmd)
Figure 6-139. DDC I2C Data Register (DDC_DATA) Reserved DDC_DATA R-0h R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 805: Ddc I2C Fifo Count Register (Ddc_Fifocnt)
FIFO data byte count (the number of bytes in the FIFO). The DDC FIFO size is 16. The maximum value for DDC_FIFOCNT is 10h. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 806: Rom Status Register (Epst)
Table 6-151. ROM Command Register (EPCM) Field Descriptions Field Value Description 31-6 Reserved Reserved LD_KSV Write before enabling again Enable loading of KSV from OTP EPCM Command: High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 807 All other values are reserved. Before writing a new value into this register, verify that the previous command is complete by checking the bit-field CMDD in the register EPST. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 808: Gamut Metadata Register (Gamut_Header1)
Indicates that the GBD will be effective on the next video field. NEXT_FIELD should be set even if the GBD is already effective (for example, Current = Affected) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 809 Table 6-154. Gamut Metadata Register (GAMUT_HEADER2) Field Descriptions (continued) Field Value Description GBD_PROFILE Transmission profile number. Values from 4h-7h are reserved. AFF_GAM_SEQ_NUM Indicates which video fields are relevant for this metadata. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 810: Gamut Metadata Register (Gamut_Header3)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-156. Gamut Metadata Registers (GAMUT_DBYTE__0-GAMUT_DBYTE__27) Field Descriptions Field Description 31-8 Reserved Reserved GAM_MDATA Gamut metadata data bytes High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 811: Hdmi_Ip_Core_Audio_Video Registers Summary
SPD InfoFrame Registers 18Ch SPD_CHSUM SPD InfoFrame Registers 190h-1F8h SPD_DBYTE__0 - SPD_DBYTE__26 SPD InfoFrame Registers 200h AUDIO_TYPE Audio InfoFrame Registers 204h AUDIO_VERS Audio InfoFrame Registers SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 812: Acr Control Register (Acr_Ctrl)
Send software-updated CTS value in N/CTS packet (for diagnostic use) 6.3.4.2 ACR Audio Frequency Register (FREQ_SVAL) The ACR audio frequency register is shown in Figure 6-148 and described in Table 6-159. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 813: Acr Audio Frequency Register (Freq_Sval)
The HDMI transmitter uses these bits to divide the MCLK input to produce CTS values according to the 128*Fs formula. The MCLK to Fs ratio is for the input Fs, not the down-sampled output Fs (see Section 6.3.4.25). SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 814: Acr N Software Value Register (N_Sval1)
Only values greater than 0 are valid. This register must be written after a hardware reset. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 815: Cts_Sval1 Field Descriptions
CTS Value for audio clock regeneration method; a 20-bit value. Diagnostic use and applied only when the CTS_SEL bit (in register ACR_CTRL) is set to 1. SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 816: Cts_Sval2 Field Descriptions
CTS Value for audio clock regeneration method; a 20-bit value. This value is RO measured and stored here by the hardware when MCLK is active and N is valid. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 817: Cts_Hval3 Field Descriptions
AUD_PAR_E Parallel audio input disabled Parallel audio input enabled SPDIF_EN S/PDIF input stream enable Disabled Enabled AUD_EN Audio input stream enable Disabled Enabled SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 818: Spdif_Ctrl Field Descriptions
Maximum sample length is 20 bits Maximum sample length is 24 bits HW_SPDIF_ Set to the FS extracted from the S/PDIF input channel status bits 24-27. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 819: Swap_I2S Field Descriptions
0b00 = Map SD0 to FIFO 0, 0b01 = Map SD1 to FIFO 0 0b10 = Map SD2 to FIFO 0, 0b11 = Map SD3 to FIFO 0 SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 820: I2S_In_Ctrl Field Descriptions
Channel Status Byte 0 6.3.4.20 I2S_CHST1 Table 6-177. I2S_CHST1 Field Descriptions Field Value Description Type 31-8 Reserved Reserved I2S_CHST1 Channel Status Byte 1: Category Code High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 821: I2S_Chst2 Field Descriptions
I2S_LEN,I2S_MAXLEN=0,I2S_MAXLEN=1 0b000,not indicated,not indicated 0b001,16,20 0b010,18,22 0b100,19,23 0b101,20,24 0b110,17,21 I2S_MAXLE Maximum audio sample word length: 0 = 20 bits, 1 = 24 bits SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 822: Asrc Field Descriptions
0b1010 = 20 bit, 0b1001 = 23 bit, 0b1000 = 19 bit, 0b0111 . 0b0110 = N/A, 0b0101 = 22 bit, 0b0100 = 18 bit, 0b0011 = N/A, 0b0010 = 16 bit, 0b0001 . 0b0000 = N/A High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 823: Hdmi_Ctrl Field Descriptions
Audio packet header layout indicator: 0b00 = Layout 0 (2-channel) , 0b01 = Layout 1 (up to 8 channels), 0b1x = Reserved HDMI_MODE HDMI Mode Disabled Enabled SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 824: Audo_Txstat Field Descriptions
6.3.4.30 AUD_PAR_BUSCLK_2 Table 6-187. AUD_PAR_BUSCLK_2 Field Descriptions Field Value Description Type 31-8 Reserved Reserved AUD_PAR_B Lower byte of integer part of parameter USCLK_2 High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 825: Aud_Par_Busclk_3 Field Descriptions
ROM (disabling loading), halts all interrupt updates, and disables the Master DDC block. Power down Normal operation PDTOT Power down total Power down everything; INT source is RSEN Normal operation SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 826: Pb_Ctrl1 Field Descriptions
Enable AVI InfoFrame transmission Disabled Enabled AVI_RPT Repeat AVI InfoFrame transmission Disabled (send once after enable bit is set) Enabled (send in every VBLANK period) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 827: Pb_Ctrl2 Field Descriptions
Enable Generic Packet transmission Disabled Enabled GEN_RPT Repeat Generic Packet transmission Disabled (send once after enable bit is set) Enabled (send in every VBLANK period) SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 828: Avi_Type Field Descriptions
AVI InfoFrame Length. AVI_HDR[23:16] 6.3.4.39 AVI_CHSUM Table 6-196. AVI_CHSUM Field Descriptions Field Value Description Type 31-8 Reserved Reserved AVI_CHSUM AVI InfoFrame Checksum. AVI_HDR[31:24] High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 829: Avi_Dbyte
SPD InfoFrame Version Code. SPD_HDR[15:8] 6.3.4.43 SPD_LEN Table 6-200. SPD_LEN Field Descriptions Field Value Description Type 31-8 Reserved Reserved SPD_LEN SPD InfoFrame Length. SPD_HDR[23:16] SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 830: Spd_Chsum Field Descriptions
AUDIO InfoFrame Type Code. AUDIO_HDR[7:0] 6.3.4.47 AUDIO_VERS Table 6-204. AUDIO_VERS Field Descriptions Field Value Description Type 31-8 Reserved Reserved AUDIO_VER AUDIO InfoFrame Version Code. AUDIO_HDR[15:8] High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 831: Audio_Len Field Descriptions
AUDIO InfoFrame Data Bytes 6.3.4.51 MPEG_TYPE Table 6-208. MPEG_TYPE Field Descriptions Field Value Description Type 31-8 Reserved Reserved MPEG_TYP MPEG InfoFrame Type Code. MPEG_HDR[7:0] SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 832: Mpeg_Vers Field Descriptions
MPEG InfoFrame Checksum. MPEG_HDR[31:24] 6.3.4.55 MPEG_DBYTE__0-MPEG_DBYTE__26 Table 6-212. MPEG_DBYTE__0-MPEG_DBYTE__26 Field Descriptions Field Value Description Type 31-8 Reserved Reserved MPEG_DAT MPEG InfoFrame Data Bytes High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 833: Gen_Dbyte
Generic Packet 2 Data Bytes 6.3.4.59 CEC_ADDR_ID Table 6-216. CEC_ADDR_ID Field Descriptions Field Value Description Type 31-8 Reserved Reserved CEC_ID CEC I2C slave address ID SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 834: Hdmi_Ip_Core_Cec Registers Summary
Table 6-219. CEC_SPEC Field Descriptions Field Value Description Type 31-8 Reserved Reserved CEC_REL CEC Specification major release CEC_REV CEC Specification minor release (rev. 1.2) High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 835: Cec_Suff Field Descriptions
Reserved Reserved STB_DUR_P Start Bit Duration Period. Measured in units of 250 µs. Expected range is 4.3 ms (11h) to 4.7 ms (12h). SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 836: Cec_Dbg_2 Field Descriptions
Field Value Description Type 31-4 Reserved Reserved CEC_INIT_ID CEC Initiator ID - needs to be written to identify this device in future transmissions. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 837: Cec_Tx_Dest Field Descriptions
Reserved CEC_TX_COM CEC Tx Command 6.3.5.13 CEC_TX_OPERAND__0-CEC_TX_OPERAND__14 Table 6-230. CEC_TX_OPERAND__0-CEC_TX_OPERAND__14 Field Descriptions Field Value Description Type 31-8 Reserved Reserved CEC_TX_COM CEC Tx Operand SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 838: Cec_Transmit_Data Field Descriptions
FIFO and acknowledged. If the command destination matches one of the bits set in this register or is a Broadcast cycle; it will be captured. High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 839: Cec_Init_Enable_0 Field Descriptions
Enable CEC_INTR2_MASK2 Short Pulse Detected Event Disable Enable CEC_INTR2_MASK1 Frame Retransmit Count Exceeded Event Disable Enable CEC_INTR2_MASK0 Start Bit Irregularity Event Disable Enable SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 840: Cec_Init_Status_0 Field Descriptions
Enable CEC_INTR2_STAT2 Short Pulse Detected Event Disable Enable CEC_INTR2_STAT1 Frame Retransmit Count Exceeded Event Disable Enable CEC_INTR2_STAT0 Start Bit Irregularity Event Disable Enable High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 841: Cec_Rx_Control Field Descriptions
CEC Destination ID - identifies the intended target of the current frame. 6.3.5.24 CEC_RX_COMMAND Table 6-241. CEC_RX_COMMAND Field Descriptions Field Value Description Type 31-8 Reserved Reserved CEC_RX_COM CEC Rx Command SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 842: Cec_Rx_Operand
Preliminary Registers www.ti.com 6.3.5.25 CEC_RX_OPERAND__0-CEC_RX_OPERAND__14 Table 6-242. CEC_RX_OPERAND__0-CEC_RX_OPERAND__14 Field Descriptions Field Value Description Type 31-8 Reserved Reserved CEC_RX_OP CEC Rx Operand High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 843: Hdmi_Phy Registers Summary
Deep color mode control. When dpcolor_ctl[1:0] 11: invalid 10: 12 bit/channel 01: 10 bit/channel 00: 8 bit/channel (default) Powerdown Control default = 1’b1; No power down 1’b0 : Phy will be power down SPRUGX9 – 15 April 2011 High-Definition Multimedia Interface (HDMI) Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 844: Bist_Cntl Field Descriptions
6.3.6.4 TMDS_CNTL9 Table 6-247. TMDS_CNTL9 Field Descriptions Field Value Description Type 31-8 Reserved Reserved ten_bit_bypass Always set this bit to 1 Reserved Reserved High-Definition Multimedia Interface (HDMI) SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 845 External components attached to the I2C bus can serially transmit/receive up to 8-bit data to/from the CPU device through the two-wire I2C interface......................... Topic Page ....................Introduction ....................Architecture ....................Registers SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 846: I2C Functional Block Diagram
Combined master transmit/receive and receive/transmit mode • Built-in FIFO size of 32 bytes for buffered read or write • Module enable/disable capability • Programmable clock generation Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 847: Multiple I2C Modules Connected
Figure 7-2. Figure 7-2. Multiple I2C Modules Connected TI device Pull-up resistors controller Serial data (I2Cx_SDA) Serial clock (I2Cx_SCL) TI device EPROM SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 848: Bit Transfer On The I2C Bus
SCL line is LOW. Figure 7-3. Bit Transfer on the I2C Bus Data line stable data I2Cx_SDA I2Cx_SCL Change of data allowed Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 849: Start And Stop Condition Events
11110XX, where XX is the two MSB of the 10-bit addresses, and 1 LSB R/nW bit, which is 0 in this case. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 850: I2C Data Transfer Formats
SCL that are generated by the master device. It does not generate the clock but it can hold clock line SCL low while intervention of the CPU is required (ROVR) following the reception of a byte. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 851: Arbitration Procedure Between Two Master Transmitters
Figure 7-8. Synchronization of Two I2C Clock Generators Wait Start HIGH state period I2Cx_SCL from device #1 I2Cx_SCL from device #2 Bus line I2Cx_SCL SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 852 CPU that it can read the amount of data left to be written and to enable the draining mechanism. (see the Draining Feature subsection for additional details). Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 853: Receive Fifo Interrupt Request Generation
CPU by writing a 1 in the corresponding interrupt flag. If the condition is still present after clearing the previous interrupt, another interrupt request will be generated. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 854: Transmit Fifo Interrupt Request Generation
Interrupt Mode. This mode is an alternative to the FIFO interrupt mode of operation, where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 855: Receive Fifo Dma Request Generation
Figure 7-12. Transmit FIFO DMA Request Generation (High Threshold) TX FIFO Max Level TXTRSH Progammable Threshold (TXTRSH) Zero Byte DMA TX Active SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 856: Transmit Fifo Dma Request Generation (Low Threshold)
I2C Core can start transferring data on the I2C bus whenever it has data in the FIFOs (FIFO is not empty). Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 857 In master mode, configure the slave address (I2C_SA = x) and the number of byte associated with the transfer (I2C_CNT = x). SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 858: I2C Registers
Section 7.3.19 I2C_CON I2C Configuration Register Section 7.3.20 I2C_OA I2C Own Address Register Section 7.3.21 I2C_SA I2C Slave Address Register Section 7.3.22 858 Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 859: Module Revision Register (Low Bytes) (I2C_Revnb_Lo)
This field changes when features are scaled up or down. This field does not change due to bug fix, or major feature change. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 860: Module Revision Register (High Bytes) (I2C_Revnb_Hi)
Spare bit to encode future schemes. 13-12 Reserved 0-3h Reads return 1h 11-0 FUNC 0-FFFh Function: Indicates a software compatible module family Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 861: System Configuration Register (I2C_Sysc)
Auto Idle mechanism is disabled Auto Idle mechanism is enabled Value after reset is high. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 862: I2C End Of Interrupt Register (I2C_Eoi)
The CPU can only clear this bit by writing a 1 into this register. A write 0 has no effect. Transmit draining inactive Transmit draining enabled Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 863 XUDF is clear when writing I2C_DATA register or resetting the I2C (I2C_CON:I2C_EN = 0). Normal operation Transmit underflow Value after reset is low. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 864 The CPU can only clear this bit by writing a 1 into this register. Writing 0 has no effect. No action Start Condition detected Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 865 RX request to the main DMA controller of the system is generated. Receive FIFO threshold not reached Receive data ready for read (RX FIFO threshold reached) Value after reset is low. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 866 The CPU can only clear this bit by writing a 1 to this register. Writing 0 has no effect. Normal operation Arbitration lost detected Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 867: I2C Status Register (I2C_Irqstatus)
Bus free AERR Access Error IRQ enabled status. No action Access error Start Condition IRQ enabled status. No action Start condition detected SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 868 Arbitration in master transmit mode, an interrupt is signaled to MPUSS. During reads, it always returns 0. Normal operation Arbitration lost detected Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 869: I2C Interrupt Enable Set Register (I2C_Irqenable_Set)
Start condition interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]. Start condition interrupt disabled Start condition interrupt enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 870 Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]. Arbitration lost interrupt disabled Arbitration lost interrupt enabled Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 871: I2C Interrupt Enable Clear Register (I2C_Irqenable_Clr)
Start condition interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]. Start condition interrupt disabled Start condition interrupt enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 872 Arbitration lost interrupt enable clear. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]. Arbitration lost interrupt disabled Arbitration lost interrupt enabled Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 873: I2C Wakeup Enable Register (I2C_We)
Receive overrun wakeup enable Receive overrun wakeup disabled Receive overrun wakeup enabled XUDF_WE Transmit underflow wakeup enable Transmit underflow wakeup disabled Transmit underflow wakeup enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 874 FIFO is full). If in the middle of such of a transaction a Not Acknowledgment event is raised, the module needs to inform CPU about transmission error. Not Acknowledge wakeup disabled Not Acknowledge wakeup enabled Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 875 Arbitration lost wakeup disabled Arbitration lost wakeup enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 876: Receive Dma Enable Set Register (I2C_Dmarxenable_Set)
Table 7-14. Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET) Field Descriptions Field Value Description 31-1 Reserved Reserved DMATX_TRANSMIT_SET Transmit DMA channel enable set. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 877: Receive Dma Enable Set Register (I2C_Dmarxenable_Clr)
Table 7-16. Transmit DMA Enable Clear Register (I2C_DMATXENABLE_CLR) Field Descriptions Field Value Description 31-1 Reserved Reserved DMARX_ENABLE_CLEAR Receive DMA channel enable clear. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 878: Receive Dma Wakeup Register (I2C_Dmarxwake_En)
General call wakeup enabled Reserved Reserved DRDY Receive/transmit data ready IRQ wakeup set. Transmit/receive data ready wakeup disabled Transmit/receive data ready wakeup enabled Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 879 No acknowledgment IRQ wakeup set. Not Acknowledge wakeup disabled Not Acknowledge wakeup enabled Arbitration lost IRQ wakeup set. Arbitration lost wakeup disabled Arbitration lost wakeup enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 880: Receive Dma Wakeup Register (I2C_Dmatxwake_En)
General call wakeup enabled Reserved Reserved DRDY Receive/transmit data ready IRQ wakeup set. Transmit/receive data ready wakeup disabled Transmit/receive data ready wakeup enabled Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 881 No acknowledgment IRQ wakeup set. Not Acknowledge wakeup disabled Not Acknowledge wakeup enabled Arbitration lost IRQ wakeup set. Arbitration lost wakeup disabled Arbitration lost wakeup enabled SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 882: System Status Register (I2C_Syss)
This bit is automatically reset by the hardware. During reads, it always returns 0. Normal mode Rx FIFO is reset Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 883 Note2: the threshold must not be changed while a transfer is in progress (after STT was configured or after the module was addressed as a slave). SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 884: Data Counter Register (I2C_Cnt)
Note2: Since for DCOUNT = 0, the transfer length is 65536, the module does not allow the possibility to initiate zero data bytes transfers. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 885: Data Access Register (I2C_Data)
In both events, the FIFO pointers are not updated and an Access Error (AERR) Interrupt is generated. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 886: I2C Configuration Register (I2C_Con)
Slave mode Master mode Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 887 SCL line is hold to 0 by the master, which can re-start a new transfer by setting the STT bit to 1. No action or stop condition detected Stop condition queried Value after reset is low SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 888: I2C Own Address Register (I2C_Oa)
0. In this case, OA [9:7] bits must be cleared to 000 by application software. Value after reset is low (all 10 bits). Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 889: I2C Own Address Register (I2C_Sa)
0. In this case, SA [9:7] bits must be cleared to 000 by application software. Value after reset is low (all 10 bits). SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 890: I2C Own Address Register (I2C_Psc)
Divide by 1 Divide by 2 Divide by 256 Value after reset is low (all 8 bits). Figure 7-37. Clock Divider ICLK SCLK 1/(PSC+1) Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 891: I2C Scl Low Time Register (I2C_Scll)
This 8-bit value is used to generate the SCL high time value (tHIGH) when the peripheral is operated in master mode. = (SCLH + 5) * I time period. HIGH Value after reset is low (all 8 bits). SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 892: System Test Register (I2C_Systest)
In slave mode, it stops during the phase transfer when 1 byte is completely transmitted/received. Free running mode Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 893 SCL line (either 1 or 0). Read:0 Read 0 from SCL line Read:1 Read 1 from SCL line Value after reset is low. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 894 SDA line and a 1 puts the I2C output driver to a high-impedance state. Write 0 to SDA line Write 1 to SDA line Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 895: I2C Buffer Status Register (I2C_Bufstat)
TX FIFO (it’s equal with the initial value of I2C_CNT.DCOUNT minus the number of data bytes already written in the TX FIFO through the OCP Interface). Value after reset is equal with 0. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 896: Own Address 1 (Oa1) (I2C_Oa1)
I2C_CON[6]) is cleared to 0. In this case, OA1 [9:7] bits must be cleared to 000 by application software. Value after reset is low (all 10 bits). Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 897: I2C Own Address 2 Register (I2C_Oa2)
I2C_CON[5]) is cleared to 0. In this case, OA2 [9:7] bits must be cleared to 000 by application software. Value after reset is low (all 10 bits). SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 898: I2C Own Address 3 Register (I2C_Oa3)
I2C_CON[4]) is cleared to 0. In this case, OA3 [9:7] bits must be cleared to 000 by application software. Value after reset is low (all 10 bits). Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 899: Active Own Address Register (I2C_Actoa)
Own address inactive Own address active Value after reset is low. SPRUGX9 – 15 April 2011 Inter-Integrated Circuit (I2C) Controller Module Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 900: I2C Clock Blocking Enable Register (I2C_Sblock)
I2C clock right after the address phase. For releasing the I2C clock the CPU must write ‘0’ in the corresponding field. I2C clock released I2C clock blocked Value after reset is low. Inter-Integrated Circuit (I2C) Controller Module SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 901 SPRUGX9 – 15 April 2011 Interrupt Controller This chapter discusses the interrupt controller......................... Topic Page ....................Introduction ....................Architecture ................Basic Programming Model ....................Registers SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 902: Interrupt Controller
GPIO. • Interrupt from peripherals inside the SOC and ARM A8. All the unmasked interrupts can generate a wake up to the interrupt controller. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 903: Interrupt Controller Block Diagram
Active Interrupt Nb, Priority Sorting Spurious Flag Control and Priority NEWFIQAGR SIR_FIQ NEWIRQAGR Priority Sorter FIQ_PRIORITY Priority Sorter SIR_IRQ IRQ_PRIORITY IRQ Input FIQ Input Processor SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 904: Arm A8 Subsystem Intc Integration
Module SCR Reset Cortex A8 Value (includes L2 Cache Functional ARM_IRQ Clock ARM_FIQ Secure INTERRUPT Mask N CONTROLLER Interrupts OCP Clock AXI-OCP Bridge L3 OCP Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 905: Interrupt Controller Resets
(register bank number: n = [0,1,2,3] for the MPU subsystem INTC, 128 incoming interrupt lines are supported). The software interrupt clears when the corresponding bit in the INTCPS_ISR_CLEARn register is written. Typical use of this feature is software debugging. SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 906 If there are any pending unmasked incoming interrupts for this interrupt request type, the INTC restarts the appropriate priority sorter; otherwise, the IRQ or FIQ interrupt line is deasserted. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 907 INTCPS_SIR_IRQ or INTCPS_SIR_FIQ register is read. SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 908 CPSR[6] = 1 /* Disable FIQ */ if high vectors configured then PC = 0xFFFF001C else PC = 0x0000001C /* execute interrupt vector */ endif Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 909 The code in steps 5 and 7 is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment.
Page 910 The priority sorting mechanism is frozen during an interrupt processing sequence. If an interrupt condition occurs during this time, the interrupt is not lost. It is sorted when the NEWIRQAGR/NEWFIQAGR bit is set (priority sorting is reactivated). Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 911: Irq/Fiq Processing Sequence
ARM Host Processor (Step 8) Restore ARM critical context. Restore the whole CPSR Return Main Program Restore the PC Execution of instruction number N + 1 SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 912 IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the IRQ line is de-asserted before IRQ/FIQ enabling. 7. Enable IRQ/FIQ at ARM side. 8. Jump to the relevant subroutine handler. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 913 The following sample code shows the previous steps: CAUTION The following code is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment.
Page 914 The following sample code shows the three previous steps: CAUTION The following code is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment.
Page 915: Nested Irq/Fiq Processing Sequence
ARM Host Processor (Step 8) Restore ARM critical context. Restore the whole CPSR Return Main Program Restore the PC Execution of instruction number N + 1 SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 916 The INTCPS_SIR_IRQ[31:7] SPURIOUSIRQFLAG bit field is a copy of the INTCPS_IRQ_PRIORITY[31:7] SPURIOUSIRQFLAG bit field. The INTCPS_SIR_FIQ[31:7] SPURIOUSFIQFLAG bit field is a copy of the INTCPS_FIQ_PRIORITY[31:7] SPURIOUSFIQFLAG bit field. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 917: Interrupt Controller (Intc) Registers
FIQ Status Register Section 8.4.19 100h + (4h × m) INTCPS_ILR0-127 Interrupt Priority Register Section 8.4.20 n = 0 to 3, m = 0 to 127 SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 918: 8.4.1 Intcps_Revision Register
The module is reset. AUTOIDLE Internal interface clock gating strategy. Interface clock is free-running. Automatic interface clock gating strategy is applied, based on the interface bus activity. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 919: 8.4.3 Intcps_Sysstatus Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-7. INTCPS_SIR_IRQ Register Field Descriptions Field Value Description 31-7 SPURIOUSIRQFLAG 0-1FF FFFFh Spurious IRQ flag ACTIVEIRQ 0-7Fh Active IRQ number SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 920: 8.4.5 Intcps_Sir_Fiq Register
Reset FIQ output and enable new FIQ generation. No effect Reset FIQ output and enable new FIQ generation. NEWIRQAGR New IRQ generation No effect Reset IRQ output and enable new IRQ generation. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 921: 8.4.7 Intcps_Protection Register
Input synchronizer clock is auto-gated based on interrupt input activity. FUNCIDLE Functional clock idle mode Functional clock gating strategy is applied. Functional clock is free-running. SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 922: 8.4.9 Intcps_Irq_Priority Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-13. INTCPS_FIQ_PRIORITY Register Field Descriptions Field Value Description 31-7 SPURIOUSFIQFLAG 0-1FF FFFFh Spurious FIQ flag FIQPRIORITY 0-7Fh Current FIQ priority Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 923: 8.4.11 Intcps_Threshold Register
LEGEND: R = Read only; -n = value after reset Table 8-15. INTCPS_ITRn Register Field Descriptions Field Value Description 31-0 ITR[n] 0-FFFF FFFFh Interrupt status before masking SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 924: Intcps_Mirn Register
Table 8-18. INTCPS_MIR_SETn Register Field Descriptions Field Value Description 31-0 MIRSET[n] Mask the interrupt [n] bits. Read returns 0. No effect. Set the MIR mask [n] bit to 1 Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 925: Intcps_Isr_Setn Register
LEGEND: R = Read only; -n = value after reset Table 8-21. INTCPS_PENDING_IRQn Register Field Descriptions Field Value Description 31-0 PENDINGIRQ 0-FFFF FFFFh IRQ status after masking. SPRUGX9 – 15 April 2011 Interrupt Controller Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 926: Intcps_Pending_Fiqn Register
Write 0 for future compatibility. Read returns reset value. FIQNIRQ Interrupt IRQ/FIQ mapping. Read returns reset value. Interrupt is routed to IRQ. Interrupt is routed to FIQ. Interrupt Controller SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 927 This chapter describes the secure digital/secure digital I/O (SD/SDIO) card interface......................... Topic Page ....................Introduction ....................Architecture ..............Low-Level Programming Models ....................Registers SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 928: Sd/Sdio1 Overview
SD_DAT2 SD_DAT3 SDMARREQN EDMA SDMAWREQN SYS CLK8 CLKADPI (192 MHz) SWAKEUP PRCM SD_SDCD SYSCLK18 SD_SDWP CLK32K (32 KHz) SD_OBl Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 929 Figure 9-2 shows the SD/SDIO1 host controller connected to an SD or SDIO card and its related external connections. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 930: Sd1 Connectivity To An Sd Card
The SD_CLK pin functions as an output but must be configured as an I/O to internally loopback the clock to time the inputs. 930 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 931: Command Token Format
32 bits. The content is protected by 7-bit CRC checksum (see Figure 9-3). Figure 9-3. Command Token Format Content 48 bits length SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 932: 48-Bit Response Packet (R1, R3, R4, R5, R6)
Figure 9-4. 48-Bit Response Packet (R1, R3, R4, R5, R6) Content 48 bits length Figure 9-5. 136-Bit Response Packet (R2) Content 136 bits length Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 933: Data Packet For Sequential Transfer (1-Bit)
This hardware reset signal has a global reset action on the module. All configuration registers and all state-machines are reset in all clock domains. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 934 The SD/SDIO host controller complies with the PRCM module handshaking protocol: • Idle request from the system power manager • Idle acknowledgment from the SD/SDIO host controller Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 935 PRCM. Moreover, in this mode, the SD/SDIO host controller unconditionally deasserts interrupts and DMA request lines are asserted. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 936: Local Power Management Features
The PRCM module has no hardware means of reading CLOCKACTIVITY settings. Thus, software must ensure consistent programming between the CLOCKACTIVITY and clock PRCM control bits. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 937 DAT line or at the end position of the CRC status in write mode. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 938 (SD_STAT[0] CC). If a response is expected but none is received, the a Command Timeout error is detected and signaled instead of the Command Complete interrupt. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 939 • There is enough space in the buffer of the SD/SDIO controller to write an entire block (BLEN writes). SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 940: 9.2.5.1.1 Dma Receive Mode
DMA read RTA = 1 into the buffer DMA request set after BLEN reached Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 941: 9.2.5.1.2 Dma Transmit Mode
SD_PSTATE[8] after first DMA the card is fully in the card WTA = 1 access written in the buffer SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 942 Figure 9-11 shows the buffer management for writing and Figure 9-12 shows the buffer management for reading. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 943: Buffer Management For A Write
Portion A Write to card 1’ Portion B 128 words are two different transfers that occur at the same time. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 944: Buffer Management For A Read
BLEN <= 2048 length Single-buffering for block length BLEN<=512 512 < BLEN <= 1024 < BLEN <= 1024 2048 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 945: Sd, Sdio Responses In The Sd_Rspxx Registers
This allows the host controller to avoid overwriting the Auto CMD12 response with the command response stored in SD_RSP10 register and vice versa. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 946: Cc And Tc Values Upon Error Detected
Busy timeout after write CRC status • Write CRC status timeout • Read data timeout • Boot acknowledge timeout Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 947: Busy Timeout For R1B, R5B Responses
- Data timeout counter is loaded and starts after CRC status. t2 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 948: Write Crc Status Timeout
- Data timeout counter is loaded and starts after Data block + CRC transmission. t4 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 949: Boot Acknowledge Timeout When Using Cmd0
- Data timeout counter is loaded and starts after Data + CRC transmission. t6 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 950: Auto Cmd12 Timing During Write Transfer
CRC status. This margin does not depend on bus configuration, DDR or standard transfer, 1,4 or 8 bus width. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 951: Auto Command 12 Timings During Read Transfer
The Auto CMD12 arrival sent by the Host controller is not sensitive to the bus configuration whether it is DDR or standard transfer and whether it is a 1,4 or 8 bit bus width transfer. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 952: Sd/Sdio Controller Transfer Stop Command Summary
NOTE: The SD/SDIO controller will send the stop command to the card on a block boundary, regardless the moment the command was written to the controller registers. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 953: Output Driven On Falling Edge
Valid OUT (Host Card) ® tMIS tMiH cmd, dat[x:0] Valid IN (Host Card) ¬ Data Sampling SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 954: Boot Mode With Cmd0
For more information on how to configure the SD/SDIO host controller, see the section titled Boot with CMD line tied to 0. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 955 (SD_SYSTEST) is used to control the signals that connect to I/O pins when the module is configured in system test (SD_CON[4] MODE = 1) mode for boundary connectivity verification. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 956: 9.2.15 Sd/Sdio Hardware Status Features
Command inhibit (CMD line) Status [0] CMDI Indicates whether issuing of command using CMD line is allowed Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 957: Global Init For Surrounding Modules
Prior to any SD register access one must enable the SD OCP clock and CLKADPI clock in PRCM module registers. Refer to the Power, Reset, and Clock Management chapter. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 958: Sd/Sdio Controller Software Reset Flow
Enable wake-up events on SD card interrupt (if SD_HCTL[24] IWE necessary). SDIO Card onlyEnable card interrupt (if necessary). SD_IE[8] CIRQENABLE Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 959: Sd/Sdio Controller Bus Configuration Flow
Clock is stable Write the SD_SYSCONFIG CLOCKACTIVITY, SIDLEMODE, and AUTOIDLE fields to configure the behavior of the module in idle mode SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 960: Sd/Sdio Controller Card Identification And Selection - Part 1
CTO = 0x1? Send a CMD0 command Set SD_SYSCTL[25] SRC bit to 0x1 and wait until it returns to 0x0 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 961: Sd/Sdio Controller Card Identification And Selection - Part 2
Is it equal to 0x1 ? (The card is busy) Send a CMD7 command (The card is not busy) *With OCR 0. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 962: Sd/Sdio Registers
ADMA System address Low bits Section 9.4.30 25Ch SD_ADMASAH ADMA System address High bits Section 9.4.31 2FCh SD_REV Versions Section 9.4.32 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 963: Sd_Hl_Rev Register
IDLEMODE FREEEMU SOFTRESET R/W-2h R/W-2h R/W-0 R/W-0 LEGENDR/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 964: System Configuration Register (Sd_Sysconfig)
(IRQ- or DMA-request-related) wake-up events when in idle state. Mode is only relevant if the appropriate IP module "swake-up" output(s) is (are) implemented. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 965 Read 0 Clocks are free-running. Write 1 Automatic clock gating strategy is applied, based on the interconnect and interface activity. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 966: System Status Register (Sd_Sysstatus)
LEGENDR/W = Read/Write; R = Read only; -n = value after reset Table 9-16. Card Status Response Error (SD_CSRE) Field Descriptions Field Value Description 31-0 CSRE Card status response error Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 967: System Test Register (Sd_Systest)
Force to 1 all status bits of the interrupt status register (SD_STAT) only if the corresponding bit field in the Interrupt signal enable register (SD_ISE) is set. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 968 If SD_SYSTEST[3] DDIR bit = 0 (output mode direction), the DAT2 line is driven high. If SD_SYSTEST[3] DDIR bit = 1 (input mode direction), no effect. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 969 The output clock is driven low. Read 1 No action. Returns 1. Write 1 The output clock is driven high. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 970: Configuration Register (Sd_Con)
SD_SYSCTL[CLKD], it is insensitive to SD_HCTL[HSPE] setting Standard modeData are transmitted on a single edge. Data Bytes and CRC are transmitted on both edges. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 971 SYSTEST register. Reserved Reserved bit field. Do not write any value. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 972 The host does not send an initialization sequence The host sends an initialization sequence Reserved Reserved bit field. Do not write any value. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 973: Power Counter Register (Sd_Pwcnt)
Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 974: Transfer Length Configuration Register (Sd_Blk)
511 bytes block length 200h 512 bytes block length 7FFh 2047 bytes block length 800h 2048 bytes block length Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 975: Command Argument Register (Sd_Arg)
Reserved ACEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGENDR/W = Read/Write; R = Read only; -n = value after reset SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 976: Command And Transfer Mode Register (Sd_Cmd) Field Descriptions
CMD39 or ACMD39 CMD40 or ACMD40 CMD41 or ACMD41 CMD42 or ACMD42 CMD43 or ACMD43 CMD44 or ACMD44 CMD45 or ACMD45 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 977 Response type. This bits defines the response type of the command. No response Response Length 136 bits Response Length 48 bits Response Length 48 bits with busy after response SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 978 DMA Enable. This bit is used to enable DMA mode for host data access. DMA mode disable DMA mode enable Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 979: Command Response[31:0] Register (Sd_Rsp10)
Table 9-25. Command Response[63:32] Register (SD_RSP32) Field Descriptions Field Value Description 31-16 RSP3 Command Response [63:48] 15-0 RSP2 Command Response [47:32] SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 980: Command Response[95:64] Register (Sd_Rsp54)
Table 9-27. Command Response[127:96] Register (SD_RSP76) Field Descriptions Field Value Description 31-16 RSP7 Command Response [127:112] 15-0 RSP6 Command Response [111:96] Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 981: Data Register (Sd_Data)
A write access to this register is allowed only when the buffer write enable status is set to 1 (SD_PSTATE[10] BWE bit), otherwise a bad access (SD_STAT[29] BADA bit) is signaled and the data is not written. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 982: Present State Register (Sd_Pstate)
(SDCD) to detect card stability. This bit is not affected by software reset. Read 0 Reset or Debouncing. Read 1 Reset or Debouncing. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 983 Issuing of command using the SD_DAT lines is allowed Read 1 Issuing of command using SD_DAT lines is not allowed SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 984 Issuing of command using SD_CMD line is allowed Read 1 Issuing of command using SD_CMD line is not allowed Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 985: Control Register (Sd_Hctl)
Disable interrupt detection at the block gap in 4-bit mode Enable interrupt detection at the block gap in 4-bit mode SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 986 0. Reserved Reserved 32-bit Address ADMA2 is selected. Reserved Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 987 1-bit Data width (SD_DAT0 used) 4-bit Data width (SD_DAT[3:0] used) Reserved Reserved bit field. Do not write any value. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 988: Sd System Control Register (Sd_Sysctl)
Reset completed Software reset for all the design 23-20 Reserved Reserved bit field. Do not write any value. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 989 The internal clock oscillates and can be automatically gated when SD_SYSCONFIG[0] AUTOIDLE bit is set to 1 (default value). SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 990: Interrupt Status Register (Sd_Stat)
Read 1 Card error Write 1 Status is cleared. 27-26 Reserved Reserved bit field. Do not write any value Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 991 Read 0 No error Write 0 Status bit unchanged Read 1 Command index error Write 1 Status is cleared. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 992 Read 0 No out-of-band interrupt Write 0 Status bit unchanged Read 1 Interrupt out-of-band occurs Write 1 Status is cleared. Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 993 Read 0 DMA Interrupt detected Write 0 Status bit unchanged Read 1 No DMA Interrupt Write 1 Status is cleared. SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 994 Read 0 No command complete Write 0 Status bit unchanged Read 1 Command complete Write 1 Status is cleared Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 995: Interrupt Sd Enable Register (Sd_Ie)
Data end bit error interrupt enable Masked Enabled DCRC_ENABLE Data CRC error interrupt enable Masked Enabled DTO_ENABLE Data timeout error interrupt enable Masked Enabled SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 996 Buffer write ready interrupt enable Masked Enabled DMA_ENABLE DMA interrupt enable Masked Enable BGE_ENABLE Block gap event interrupt enable Masked Enabled Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 997 Table 9-33. Interrupt SD Enable Register (SD_IE) Field Descriptions (continued) Field Value Description TC_ENABLE Transfer completed interrupt enable Masked Enabled CC_ENABLE Command completed interrupt enable Masked Enabled SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 998: Interrupt Signal Enable Register (Sd_Ise)
The host controller provides the clock to the card until the card sends the data or the transfer is aborted. Enabled Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 999 Buffer write ready signal status enable Masked Enabled DMA_SIGEN DMA signal status enable Masked Enabled BGE_SIGEN Block gap event signal status enable Masked Enabled SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface Submit Documentation Feedback © 2011, Texas Instruments Incorporated...
Page 1000 Value Description TC_SIGEN Transfer completed signal status enable Masked Enabled CC_SIGEN Command completed signal status enable Masked Enabled 1000 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface SPRUGX9 – 15 April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...