Interrupt Source Register (Intr4); Interrupt Unmask Register (Int_Unmask1); Interrupt Source Register (Intr4) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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6.3.2.83 Interrupt Source Register (INTR4)

The interrupt source register is shown in
31
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-114. Interrupt Source Register (INTR4) Field Descriptions
Bit Field
31-4 Reserved
3 REG_INTR4_STAT3
2 REG_INTR4_STAT2
1 REG_INTR4_STAT1
0 DSD_INVALID

6.3.2.84 Interrupt Unmask Register (INT_UNMASK1)

The interrupt unmask register is shown in
31
15
7 6
SOFT HPD
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUGX9 – 15 April 2011
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Preliminary
Figure 6-105
Figure 6-105. Interrupt Source Register (INTR4)
4
R-0h
Value Description
Reserved
CEC interrupt
For each interrupt bit:
0 No interrupt occurred. Write any bit to 1 to clear the bit and the interrupt.
1 Interrupt asserted
For each interrupt bit:
0 No interrupt occurred. Write any bit to 1 to clear the bit and the interrupt.
1 Interrupt asserted
DSD stream got invalid sequence: more then 24 bits of the same value. Asserted if set to 1.
Write 1 to clear
Figure 6-106
Figure 6-106. Interrupt Unmask Register (INT_UNMASK1)
5 4
RSEN DROP_SAMPL BIP_HASE_ER
E
R/W-0h R/W-0h
© 2011, Texas Instruments Incorporated
and described in
Reserved
R-0h
Reserved
R-0h
3 2
REG_INTR4_ REG_INTR4_
STAT3 STAT2
RW1toClr-0h RW1toClr-0h
and described in
Reserved
R-0h
Reserved
R-0h
3 2
RI_128
R
R/W-0h R/W-0h
High-Definition Multimedia Interface (HDMI)
Registers
Table 6-114.
1
REG_INTR4_ DSD_
STAT1 INVALID
RW1toClr-0h RW1toClr-0h
Table 6-115.
1
OVER_RUN UNDER_RUN
R/W-0h R/W-0h
16
8
0
16
8
0
785