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Architecture
8.2.3.2
Masking
8.2.3.2.1 Individual Masking
Detection of interrupts on each incoming interrupt line can be enabled or disabled independently by the
INTCPS_MIRn interrupt mask register. In response to an unmasked incoming interrupt, the INTC can
generate one of two types of interrupt requests to the processor:
•
IRQ: low-priority interrupt request
•
FIQ: fast interrupt request
The type of interrupt request is determined by the INTCPS_ILRm[0] FIQNIRQ bit (m= [0,127]). The
current incoming interrupt status before masking is readable from the INTCPS_ITRn register. After
masking and IRQ/FIQ selection, and before priority sorting is done, the interrupt status is readable from
the INTCPS_PENDING_IRQn and INTCPS_PENDING_FIQn registers.
8.2.3.2.2 Priority Masking
To enable faster processing of high-priority interrupts, a programmable priority masking threshold is
provided (the INTCPS_THRESHOLD[7:0] PRIORITYTHRESHOLD field). This priority threshold allows
preemption by higher priority interrupts; all interrupts of lower or equal priority than the threshold are
masked. However, priority 0 can never be masked by this threshold; a priority threshold of 0 is treated
the same way as priority 1. PRIORITY and PRIORITYTHRESHOLD fields values can be set between 0
and 7Fh; 0 is the highest priority and 7Fh is the lowest priority. When priority masking is not necessary,
a priority threshold value of FFh disables the priority threshold mechanism. This value is also the reset
default for backward compatibility with previous versions of the INTC.
8.2.3.3
Priority Sorting
A priority level (0 being the highest) is assigned to each incoming interrupt line. Both the priority level
and the interrupt request type are configured by the INTCPS_ILRm register. If more than one incoming
interrupt with the same priority level and interrupt request type occur simultaneously, the
highest-numbered interrupt is serviced first. When one or more unmasked incoming interrupts are
detected, the INTC separates between IRQ and FIQ using the corresponding INTCPS_ILRm[0]
FIQNIRQ bit. The result is placed in INTCPS_PENDING_IRQn or INTCPS_PENDING_FIQn. If no other
interrupts are currently being processed, INTC asserts IRQ/FIQ and starts the priority computation.
Priority sorting for IRQ and FIQ can execute in parallel. Each IRQ/FIQ priority sorter determines the
highest priority interrupt number. Each priority number is placed in the corresponding
INTCPS_SIR_IRQ[6:0] ACTIVEIRQ field or INTCPS_SIR_FIQ[6:0] ACTIVEFIQ field. The value is
preserved until the corresponding INTCPS_CONTROL NEWIRQAGR or NEWFIQAGR bit is set. Once
the interrupting peripheral device has been serviced and the incoming interrupt deasserted, you must
write to the appropriate NEWIRQAGR or NEWFIQAGR bit to indicate to the INTC the interrupt has
been handled. If there are any pending unmasked incoming interrupts for this interrupt request type, the
INTC restarts the appropriate priority sorter; otherwise, the IRQ or FIQ interrupt line is deasserted.
906
Interrupt Controller
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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