Cm_Alwon_Rtc_Clkstctrl Register; Cm_Alwon_Rtc_Clkstctrl Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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14.7.11.12 CM_ALWON_RTC_CLKSTCTRL Register

The CM_ALWON_RTC_CLKSTCTRL register enables the domain power state transition. It controls the
software supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It
also hold one status bit per clock input of the domain.
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-107. CM_ALWON_RTC_CLKSTCTRL Register Field Descriptions
Bit Field
31-9 Reserved
8 CLKACTIVITY_RTC_GCLK
7-2 Reserved
1-0 CLKTRCTRL
SPRUGX9 – 15 April 2011
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Preliminary
Figure 14-92. CM_ALWON_RTC_CLKSTCTRL Register
R-0
Value Description
0 Reserved
This field indicates the state of the RTC_GCLK clock in the domain.
0 Corresponding clock is gated
1 Corresponding clock is active
0 Reserved
Controls the clock state transition of the RTC clock domain in Always ON
power domain.
0 Reserved
1h Reserved
2h SW_WKUP: Start a software forced wake-up transition on the domain.
3h Reserved
© 2011, Texas Instruments Incorporated
9 8
CLKACTIVITY_RTC_GCLK
R-0
Power, Reset, and Clock Management (PRCM) Module
Registers
7 2 1 0
Reserved CLKTRCTRL
R-0 R-2h
1489