Cm_Default_L3_Fast_Clkstctrl Register; Cm_Default_L3_Fast_Clkstctrl Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

14.7.6.2 CM_DEFAULT_L3_FAST_CLKSTCTRL Register

The CM_DEFAULT_L3_FAST_CLKSTCTRL register enables the domain power state transition. It
controls the software supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE
states. It also holds one status bit per clock input of the domain.
31
15 10
Reserved CLKACTIVITY_DDR_GCLK
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-70. CM_DEFAULT_L3_FAST_CLKSTCTRL Register Field Descriptions
Bit Field
31-10 Reserved
9 CLKACTIVITY_DDR_GCLK
8 CLKACTIVITY_L3_FAST_GCLK
7-2 Reserved
1-0 CLKTRCTRL
1454
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Figure 14-55. CM_DEFAULT_L3_FAST_CLKSTCTRL Register
Reserved
9
CLKACTIVITY_L3_FAST_GCLK
R-0
Value
0
0
1
0
1
0
0
1h
2h
3h
© 2011, Texas Instruments Incorporated
R-0
8
R-0
Description
Reserved
This field indicates the state of the DDR_GCLK clock in the domain.
Corresponding clock is gated
Corresponding clock is active
This field indicates the state of the L3_FAST_GCLK clock in the
domain.
Corresponding clock is gated
Corresponding clock is active
Reserved
Controls the clock state transition of the L3_FAST clock domain in
DEFAULT power domain.
Reserved
SW_SLEEP: Start a software forced sleep transition on the domain.
SW_WKUP: Start a software forced wake-up transition on the
domain.
Reserved
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7 2 1
Reserved CLKTRCTRL
R-0 R/W-1
SPRUGX9 – 15 April 2011
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