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13.4.7.6 MEMSPACE Register
The memory limit and base register (MEMSPACE) is described in the figure and table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-20
Memory Limit
0-FFFh Memory Limit Address
19-16
Reserved
15-4
Memory Base
0-FFFh Memory Base Address
3-0
Reserved
13.4.7.7 PREFETCH_MEM Register
The prefetchable memory limit and base register (PREFETCH_MEM) is described in the figure and
table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-20
End Address
0-FFFh Upper 12 bits of 32 bit Prefetchable Memory End Address
19-17
Reserved
16
Memory
Addressing
15-4
Start Address
0-FFFh Upper 12 bits of 32 bit Prefetchable Memory Start Address
3-1
Reserved
0
Memory
Addressing
SPRUGX9 – 15 April 2011
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Preliminary
Figure 13-97. MEMSPACE Register
Memory Limit
R/W-0
Memory Base
R/W-0
Table 13-103. MEMSPACE Register Field Descriptions
Value
Description
0
Reserved
0
Reserved
Figure 13-98. PREFETCH_MEM Register
End Address
R/W-0
Start Address
R/W-0
Table 13-104. PREFETCH_MEM Register Field Descriptions
Value
Description
0
Reserved
Memory addressing. Writable from internal bus interface.
0
32 bit memory addressing
1
64 bit memory addressing
0
Reserved
Memory addressing. Writable from internal bus interface.
0
32 bit memory addressing
1
64 bit memory addressing
© 2011, Texas Instruments Incorporated
20
19
4
3
20
19
Reserved
R-0
4
3
Reserved
R-0
Peripheral Component Interconnect Express (PCIe)
Registers
16
Reserved
R-0
0
Reserved
R-0
17
16
Memory
Addressing
R-0
1
0
Memory
Addressing
R-0
1359
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