2.5 Volt Decoupling Requirements; Ddr Vterm Plane - Intel Pentium M Processor Design Manual

Figure 52.

DDR VTerm Plane

1.25V Vterm Fill
One Rtt per signal
1.25V
Vterm Fill
Ground Fill
on Top Layer
Two Vias Per 1
Capacitor to the
Internal Ground
6.3.8

2.5 Volt Decoupling Requirements

Decouple the DIMM connectors as shown in
(0603) capacitors between each pair of DIMM connectors. Place two Tantalum 100 µF capacitors
around each DIMM connector and two additional Tantalum 100 µF capacitors per channel, keeping
them within 0.5 inch of the DIMM connectors.
decoupling scheme and
DIMMs per channel may be used, continue the decoupling scheme for each additional DIMM
connector.
Design Guide
®
Intel Pentium
Two Vias Per 1 Capacitor
to the Internal Ground
Plane
Furthest DIMM from Intel
50 mils
minimum
Plane
Figure 54 depicts a 2-DIMM per channel decoupling scheme. When more
®
M Processor and Intel
Memory Interface Routing Guidelines
Ground Fill on
Top Layer
One 0.1 µF Decoupling
Capacitor per 2 Termination
Resistors or (2 Caps/Rpack)
®
MCH
DIMM
DIMM
Figure 53 or Figure
Figure 53 depicts a 1-DIMM per channel
®
E7501 Chipset Platform
50 mils
minimum
0.5" max
One 100 µF Tantalum
Capacitor at Each End
of Each Island
One 0.1 µF
decoupling
capacitor per 2
termination
resistors
54. Place six ceramic 0.1 µF
91