Configuration - LAPIS Semiconductor ML62Q1000 Series User Manual

Table of Contents

Configuration

Figure 23-1 shows the configuration of SA-ADC.

: SA-ADC control register

SADEN0/1 : SA-ADC enable register 0,1

: SA-ADC mode register

: SA-ADC scan conversion interval setting register

: SA-ADC result register

: SA-ADC result register n (n = 0 to 15, 16)

SADLMOD : SA-ADC upper/lower limit mode register

: SA-ADC upper limit setting register

: SA-ADC lower limit setting register

: SA-ADC upper/lower limit status registern n (n=0,1)

VREFCON : reference voltage control register

SADTMOD : SA-ADC test mode register

: SA-ADC interrupt request

Successive approximation type A/D convertor DMA request

: SA-ADC trigger register

Figure 23-1 Configuration of successive approximation type A/D Converter

Chapter 23 Successive Approximation Type A/D Converter

SADCON, SADEN0/1

SADMOD, SADSTM

ML62Q1000 Series User's Manual

approximation

Show Quick Links

Table of Contents