LAPIS Semiconductor ML62Q1000 Series User Manual page 476

Table of Contents

Advertisement

Bit symbol
Bit no.
name
4
I2US0TR
3
I2US0SAA
2
I2US0ER
1
I2US0ACR
0
I2US0BB
[Note]
Ÿ
Do not update each bit of the I2UM0STA register by using the bit symbol. Update it by using a byte
access, not so that unintented bits are changed by the bit access instructions.
FEUL62Q1000
This bit is used to indicate the transmitting or receiving state in the slave mode.
This bit is set to "1" when detecting the I2UM0RW bit of I2UM0SA register is "1" (data
received mode). This bit is reset to "0" when detecting a stop condition or detecting the
I2UM0RW bit is "0" (data transmission mode).
To reset the I2US0TR bit not in the case detecting a stop condition, write "1" to this bit or write
"0" to I2US0EN bit of I2US0MD register.
0: Receiving state (Initial value)
1: Transmitting state
This bit is used to indicate that this device is specified as a slave address in the slave mode.
This bit is set to "1" when the content of the slave address output by the master device
coincides with the contents of I2US0SA register. This bit is reset to "0" when a stop condition
is received.
To reset the I2US0SAA bit, write "1" to this bit or write "0" to I2US0EN bit of I2US0MD
register.
0:
Not coincide with the slave address (initial value)
1:
Coincides with the slave address
This bit is used to indicate a transmission error in the slave mode.
When the value of the bit transmitted and the value of the I2CU0_SDA pin do not coincide,
this bit is set to "1". When this bit is set to "1", the I2CU0_SDA pin output is disabled until the
subsequent byte data communication terminates.
To reset the I2US0ER bit, write "1" to this bit or write "0" to I2US0EN bit of I2US0MD register.
0:
There was no transmission error (initial value)
1:
There was a transmission error
This bit is used to store an acknowledgment signal received in the slave mode.
The acknowledgment signals are received each time the slave address is received and data
transmission or reception is completed.
To reset the I2US0ACR bit, write "1" to this bit or write "0" to I2US0EN bit of I2US0MD
register.
0:
Received the acknowledgment "0" (initial value)
1:
Received the acknowledgment "1"
This bit is used to indicate the state of use of the I
When the start condition is generated on the I
condition is generated, this bit is reset to "0".
To reset the I2US0BB bit, write "1" to this bit or write "0" to I2US0EN bit of I2US0MD register.
2
0: I
C bus-free state (initial value)
2
1: I
C bus-busy state
ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
Description
2
C bus in the slave mode.
2
C bus, this bit is set to "1" and when the stop
12-20

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents