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SnEN
SUn_SCLK
SUn_SIN
Shift register
SUnRC0
SIUn0INT
Write SDnBUF
SnFUL
SnRXF
SnRFUL
Figure 11-8 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (Positive Logic)
SnEN
SUn_SCLK
SUn_SIN
Shift register
SUnRC0
SIUn0INT
Write SDnBUF
SnFUL
SnRXF
SnRFUL
Figure 11-9 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (Negative Logic)
FEUL62Q1000
7
6
5
4
7
6
5
4
When an interrupt at the start of reception is set
When an interrupt at the end of reception is set
(8-Bit Length, MSB First)
7
6
5
4
7
6
5
4
When an interrupt at the start of reception is set
When an interrupt at the end of reception is set
(8-Bit Length, MSB First)
ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
3
2
1
0
3
2
1
Receive data
3
2
1
0
3
2
1
0
0
Receive data
11-39
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