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WDT counter value
Overflow
period (T
)
WOV
0
The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is 1.024kHz)
before the WDT gets overflowed. Design the WDT clear timing with time to spare.
Figure 10-7 Example of Operation Timing in Window Function Disabled mode (When Overflow Period=8000 ms)
FEUL62Q1000
WDT cleared
WDT cleared
(enabled)
7999 ms
7998 ms
8000 ms
WDT
interrupt generated
(disabled)
8000 ms
ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
Time
WDT
reset generated
10-14
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