LAPIS Semiconductor ML62Q1000 Series User Manual page 877

See Section 23.3.3 "A/D Conversion Time Setting".
[ ] If choosing to start A/D conversion after discharging the internal sample hold capacitive electrical
charge to the VSS level at the start of A/D conversion, the A/D conversion time shown in Table 23-3 and
23-4 is increased by two clocks of the conversion clock (SAD_CLK).
[ ] The A/D conversion time does not include the clock frequency error.
See Section 23.4 "Notes on SA-ADC".
[ ] Check the notes for using the Successive Approximation Type A/D Converter.
Chapter 24 Regulator
See Section 24.1.3 "List of Pins".
[ ] In order to improve the noise resistance, place the inter-power supply bypass capacitor (CV=1 μF or
larger) and the the internal logic voltage (VDDL) capacitor (CL: 1 μF) in the vicinity of LSI on the user
board using the shortest possible wiring without passing through via holes.
[ ] The internal logic voltage (VDDL) is unavailable to use for an external device voltage.
Chapter 25 Flash Memory
See Section 25.2.2 "Flash Address Register (FLASHA)".
[ ] Note that programming for the program memory space is performed by the unit of 4 bytes. In this case,
the setting values in the FA1 bit and FA0 bit are ignored.
See Section 25.2.4 "Flash Data Register 0 (FLASHD0)".
[ ] Write data into FLASHD0 register at first and FLASHD1 register the second.
[ ] Data written into FLASHD0H register and FLASHD1 register are invalid.
[ ] Specify a segment address to the FLASHSEG at first, because it determines whether the programming
is for program memory space or data flash memory.
[ ] Back Ground Operation(BGO) function allows CPU continue running the program codes while
programming the data flash memory. Confirm the end of programming by checking FDPRSTA bit of
Flash Status Register(FLASHSTA).
[ ] Erase data in the addresses in advance. Programmed data without erase is unguaranteed.
[ ] Do not read or program unused areas to prevent the CPU works incorrectly.
See Section 25.2.5 "Flash Data Register 1 (FLASHD1)".
[ ] Specify a segment address to the FLASHSEG at first, because it determines whether the programming
is for program memory space or data flash memory.
See Section 25.2.7 "Flash Acceptor (FLASHACP)".
[ ] Even if other instructions are executed between the instruction that writes "0FAH" and "0F5H" to the
FLASHACP, the erasing or programming function is still valid.
[ ] If data other than "0F5H" is written to the FLASHACP after "0FAH" is written, "0FAH" becomes invalid.
In this case, it needs to write "0FAH" again.
See Section 25.2.9 "Flash Status Register (FLASHSTA)".
[ ] Perform the erasing or programming after checking the FDERSTA bit or FDPRSTA bit are "0". The
erasing or programming becomes invalid when either the FDERSTA bit or the FDPRSTA bit is "1".
See Section 25.3 "Self-programming".
[ ] Erase the area to be reprogrammed (data programmed without erasing is unguaranteed).
[ ] Before programming the user program, prepare a program for self-programming in the program code
area which is not erased/reprogrammed.
See Section 25.3.1 "Notes on Debugging Self-programming Code".
[ ] Do not perform the real time execution with break points set in the scope of program for
self-programming (from setting the flash acceptor to setting the flash data register). Otherwise, the flash
memory may not be reprogrammed if break points occur within the scope of program for
self-programming.
[ ] Do not perform the step execution within the scope of program for self-programming. Otherwise, the
flash memory may not be reprogrammed if the step execution is performed within the scope of program
for self-programming.
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-18