LAPIS Semiconductor ML62Q1000 Series User Manual page 602

[Note]
Ÿ
In the STOP/STOP-D/HALT-H
PI0SM bits of EIMOD0 register since the sampling clock stops. When choosing "with sampling" and
entering the STOP/STOP-D/HALT-H
When entering to STOP/STOP-D/HALT-H
After returning from STOP/STOP-D/HALT-H
if
needed.
When returning from STOP/STOP-D/HALT-H
(LSCLK or HSCLK) starts to be supplied. The start-up time for supplying clock is dependent of the clock
or register settings. For details about it, see Table 4-5 "Wake-up Time from Standby Mode" in the Chapter
4 "Power Management".
Ÿ
When the HSCLK is chosen and ENOSC bit of FCON register is "0", the sampling function is not
available.
Ÿ
When the HSCLK is chosen for the sampling block and the high-speed clock is not oscillating, the
sampling circuit does not work. Enable the high-speed clock oscillation in advance if sampling with the
HSCLK. For how to enable the high-speed clock oscillation, see Chapter 6 "Clock Generation Circuit".
*1
HALT-H in the case the high-speed clock is chosen
*2
When entering STOP/STOP-D/HALT-H
When returning from STOP/STOP-D mode, the interrupt is disable until the sampling clock (LSCLK)
starts to be supplied. The start-up time for supplying clock is dependent of the clock or register settings.
For details about it, see Table 4-5 "Wake-up Time from Standby Mode" in the Chapter 4 "Power
Management".
FEUL62Q1000
(*1)
mode, no sampling is performed regardless of the values set in PI7SM to
(*1)
, there is a time period
(*1)
mode, specify the external interrupt as "without sampling".
(*1)
mode, specify the PI7SM to PI0SM bits as "with sampling"
(*1)
mode, the interrupt is disable until the sampling clock
(*1)
mode: Max.30us
ML62Q1000 Series User's Manual
Chapter 18 External Interrupt Function
(*2)
in which interrupts gets disabled.
18-8