LAPIS Semiconductor ML62Q1000 Series User Manual page 376

9.3.7.2 Start/Stop Operations by Event Trigger
Here is the setting used to control the counter by event triggers.
First, before controlling the counter, set the following configuration by FTnTRG0 and FTnTRG1 registers.
Choose "no division" as the timer clock.
If using HSCLK as the system clock, write "1" to the FTnCK0 bit of the FTnCLK register, and "000" to FTnCKD2 to
FTnCKD0 bits.
Setting the FTnTRG0 register
- Enable/disable counter start/stop with event triggers
- Clear/not clear the counter when starting/stopping with event triggers
- Accept/not accept the next counter start after stopping with event triggers
- Accept/not accept the counter clear if the Positive phase output is "H" level when clearing the counter with event
triggers.
- Event trigger source (EXTRG0 to EXTRG7, TMH0TRG to TMH5TRG, FTMnTRG, CMP0D)
Setting the FTnTRG1 register
The edge/level of the event trigger causing counter start
The edge/level of the event trigger causing counter stop
Setting the timer clock used
Choose the timer clock in the FTnCLK register.
(Even if not changing the setting, choose the timer clock again.)
Once the configuration above is completed, control the counter by the FTCSTR register. The procedure is as follows:
(1) Make the waiting state for an event trigger
Write "1" to the FTnETG bit to make the waiting state for an event trigger (if the level setting is applied for
trigger start and the level is applicable, the counter operation is started as soon as the FTnTGEN bit of the
FTCSTAT register becomes "1".)
(2) Start the timer counting by the software
If writing "1" to the FTnETG bit, and writing "1" to the FTnSTR bit with the trigger operation enabled, the
timer counting is started by the software.
If writing "0" to the FTnSTP bit of the FTCSTP register while counter operation is in progress, the timer
counting is stopped by the software.
If EXTRG0 to EXTRG7 and CMP0D are chosen as the event trigger source, input the signal with the noise removal
width set in FTnTRF2 to FTnTRF0 bits of the FTnTRG1 register or longer. Even when the noise filter is disabled in
FTnTRF2 to FTnTRF0 bits, pulse of one clock or less may sometimes be removed, sometimes not.
Figure 9-16 shows the sampling timing for the external input.
Sampling clock
Counting clock
External input pin
Waveform after removing
FEUL62Q1000
Figure 9-16 Sampling Timing for the External Input
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
FTMn accepts the external input
9-56