LAPIS Semiconductor ML62Q1000 Series User Manual page 670

Figure 22-6 shows an example of the operation timing chart when the VLS0 interrupt output with sampling is specified.
VLS0EN bit
Threshold voltage (at rise)
VLS0 comparator
comparison result
Sampling clock
VLS0 interrupt
Figure 22-6 Operation Timing Diagram When the VLS0 Interrupt Output with Sampling is specified
The operation shown in Figure 22-6 is described below:
(1) Choose a detection voltage by the VLS0LV3 to VLS0LV0 bits of the VLS0LV register.
(2) Choose "Sampling with HSCLK" or "Sampling with LSCLK" by the VLS0SM1 and VLS0SM0 bits of the
VLS0SMP register.
(3) Write "0x02" or "0x03" to VLS0AMD[1:0] bits of VLS0MOD register in order to choose the supervisor mode.
(4) Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register.
(5) Write "1" to the VLS0EN bit to enable VLS0 operation.
(6) Wait until the comparison result of the VLS0 comparator is stabilized.
(7) V becomes below the threshold voltage (V
DD
(8) Once the comparison result of the VLS0 comparator is stabilized, the VLS0RF bit is set to "1" after three cycles of
the sampling clock.
(9) If the comparison result of the VLS0 comparator is below the threshold voltage (V
continues for the duration of three cycles or more of the sampling clock, the VLS0F bit is set to "1" and the VLS0
interrupt is generated.
(10) The comparison result of the VLS0 comparator becomes equal to or above the threshold voltage (V
(11) If the comparison result of the VLS0 comparator is equal to or above the threshold voltage (V
condition continues for the duration of three cycles or more of the sampling clock, the VLS0F bit is cleared to "0"
and the VLS0 interrupt is generated.
(12) Write "0" to the VLS0EN bit to disable VLS0 operation.
[Note]
Ÿ
Entering the STOP/STOP-D mode is not allowed during the VLS0 stabilization time. If entering the
STOP/STOP-D mode after the supervisor mode is enabled, make sure that the VLS0RF bit is set to "1",
then enter the STOP/STOP-D mode.
Ÿ
When VLS0 is stopped (VLS0EN bit="0") while the VDD is lower than the specified threshold voltage
(VLS0F bit="1"), the VLS0 interrupt is generated.
FEUL62Q1000
(1)~(5)
↓
VLS0RF
V
DD
(at fall)
Stabilization
VLS0F
(6) (7)
↓ ↓
time
).
VLSF
ML62Q1000 Series User's Manual
Chapter 22 Voltage Level Supervisor
(8) (9) (10)
↓ ↓ ↓
V
VLSR
V
VLSF
V
SS
) and this condition
VLSF
VLSR
(11) (12)
↓
↓
).
VLSR
) and this
22-15