LAPIS Semiconductor ML62Q1000 Series User Manual page 400

The following table shows WDT counter clear enabled periods.
If the overflow period of the WDT counter is set to 62.5 ms or less in WDT2 to 0 bits, the window function is disabled
regardless of setting values of WOVF1 and WOVF0 bits.
WDT2 WDT1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
*1: Time when the WDTCLK is 1 .024kHz. For the WDTCLK, select LSCLK through the code option.
*2: The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is 1.024kHz) before the
WDT gets overflowed.
Table 10-5 WDT Counter Clear Enabled Period in Window Function Enabled Mode 2
WDT2 WDT1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
*1: Time when the WDTCLK is 1 .024kHz. For the WDTCLK, select LSCLK through the code option.
*2: The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is 1.024kHz)
before the WDT gets overflowed.
[Note]
Ÿ
When using the window function enabled mode, always define a WDT interrupt function even though no
WDT interrupt occurs. For providing the fail-safe, it is recommended to generate the WDT invalid clear
reset by forcibly clearing the WDT in the WDT interrupt function.
Ÿ
When using the window function enabled mode, choose "the clock with divided frequency of low-speed
oscillation clock (32.768 kHz)" for the WDT count clock with the code option. If "WDT RC1K oscillation
clock" is chosen, this function is unusable because the frequency has a significant error.
FEUL62Q1000
Table 10-4 WDT Clear Enabled Period in Window Function Enabled Mode 1
Overflow
WDT0
period (T
WOV
Approx. 7.8 ms
0
Approx. 15.6 ms
1
Approx. 31.3 ms
0
Approx. 62.5 ms
1
Approx. 125 ms
0
Approx. 500 ms
1
Approx. 2000 ms
0
Approx. 8000 ms
1
Overflow
WDT0
period (T
WOV
Approx. 7.8 ms
0
Approx. 15.6 ms
1
Approx. 31.3 ms
0
Approx. 62.5 ms
1
Approx. 125 ms
0
Approx. 500 ms
1
Approx. 2000 ms
0
Approx. 8000 ms
1
WDT reset
WDT clear enabled period (T
*1 *1
) generation time
Approx. 7.8 ms
Approx. 15.6 ms
Approx. 31.3 ms
Approx. 62.5 ms
Approx. 125 ms
Approx. 500 ms
Approx. 2000 ms
Approx. 8000 ms
WDT reset
*1 *1
) generation time
Approx. 7.8 ms
Approx. 15.6 ms
Approx. 31.3 ms
Approx. 62.5 ms
Approx. 125 ms
Approx. 500 ms
Approx. 2000 ms
Approx. 8000 ms
ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
WCL
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ 75% of overflow period
≈ 75% of overflow period
≈ 75% of overflow period
≈ 75% of overflow period
WDT clear enabled period
*1*2
(T )
WCL
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ Overflow period
≈ 50% of overflow period
≈ 50% of overflow period
≈ 50% of overflow period
≈ 50% of overflow period
*1*2
)
10-18