Page 1 FEUL610Q174-02 ML610Q174 User’s Manual Issue Date: Aug. 31, 2018...
Page 2: Feul610Q174
Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
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ML610Q174 User’s manual Preface This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q174. The following manuals are also available. Read them as necessary.  nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U8/100 Core ...
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ML610Q174 User’s manual Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦...
Page 5: Table Of Contents
Configuration of Functional Blocks ......................1-4 1.2.1 Block Diagram of ML610Q174 ......................1-4 Pins ................................1-5 1.3.1 Pin Layout ............................. 1-5 1.3.1.1 Pin Layout of ML610Q174 QFP Package ..................1-5 1.3.2 List of Pins ............................1-6 1.3.3 Pin Description ............................1-9 1.3.4 Termination of Unused Pins ........................
Page 6 ML610Q174 User’s Manual Table of Contents 4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock ............4-12 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock ............4-13 4.3.3.3 Note on Return Operation from STOP/HALT Mode ..............4-14 4.3.4 Block control function ......................... 4-15 Chapter 5 Interrupts (INTs) .............................
Page 7 ML610Q174 User’s Manual Table of Contents 6.3.3 Switching of System Clock ......................... 6-14 Register setup of the port .......................... 6-15 6.4.1 When the P21 pin (OUTCLK:output) operates as the high-speed clock output function ....6-15 6.4.2 When the P20 pin (LSCLK:output) operates as the low-speed clock output function ......6-16 6.4.3...
Page 8 ML610Q174 User’s Manual Table of Contents Chapter 9 Watchdog Timer ............................. 9-1 Overview ..............................9-1 9.1.1 Features ..............................9-1 9.1.2 Configuration ............................9-1 Description of Registers ..........................9-2 9.2.1 List of Registers ............................ 9-2 9.2.2 Watchdog Timer Control Register (WDTCON) ................... 9-3 9.2.3...
Page 9 ML610Q174 User’s Manual Table of Contents 10.3.8 Emergency Stop Operation ....................... 10-58 10.4 Specifying Port Registers ........................10-60 10.4.1 Functioning P34 Pin (PWM4) as PWM Output ................10-60 10.4.2 Functioning P43 Pin (PWM4) as PWM Output ................10-61 10.4.3 Functioning P35 Pin (PWM5) as PWM Output ................10-62 10.4.4 Functioning P47 Pin (PWM5) as PWM Output ................
Page 10 ML610Q174 User’s Manual Table of Contents 12.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) ............12-12 12.2.12 UART0 Status Register (UA0STAT) ....................12-13 12.2.13 UART1 Status Register (UA1STAT) ....................12-15 12.3 Description of Operation......................... 12-17 12.3.1 Transfer Data Format ........................12-17 12.3.2 Baud Rate ............................
Page 11 ML610Q174 User’s Manual Table of Contents 14.2 Description of Registers ..........................14-3 14.2.1 List of Registers ..........................14-3 14.2.2 Port 0 Data Register (P0D) ......................... 14-4 14.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) ................14-5 14.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) ............. 14-6 14.2.5 External Interrupt Control Register 2 (EXICON2) ................
Page 12 ML610Q174 User’s Manual Table of Contents Chapter 18 18. Port 4 ................................18-1 18.1 Overview ..............................18-1 18.1.1 Features ............................... 18-1 18.1.2 Configuration ............................18-1 18.1.3 List of Pins ............................18-2 18.2 Description of Registers ..........................18-3 18.2.1 List of Registers ..........................18-3 18.2.2 Port 4 Data Register (P4D) .........................
Page 13 ML610Q174 User’s Manual Table of Contents 21.2.4 Port 9 Control Registers 0, 1 (P9CON0, P9CON1) ................21-4 21.3 Description of Operation........................... 21-5 21.3.1 Output Port Functions ......................... 21-5 Chapter 22 22. Port C ................................22-1 22.1 Overview ..............................22-1 22.1.1 Features ............................... 22-1 22.1.2 Configuration ............................
Page 14 ML610Q174 User’s Manual Table of Contents 25.1.2 Configuration of the LCD Drivers....................... 25-2 25.1.3 Configuration of the LCD drive voltage control circuit ..............25-3 25.1.4 List of Pins ............................25-4 25.2 Description of Registers ..........................25-5 25.2.1 List of Registers ..........................25-5 25.2.2 Bias Circuit Control Register 0 (BIASCON) ..................
Page 15 ML610Q174 User’s Manual Table of Contents 26.2.35 SA-ADC Control Register 1 (SADCON1) ..................26-17 26.2.36 SA-ADC Mode Register 0 (SADMOD0) ..................26-18 26.2.37 SA-ADC Mode Register 1 (SADMOD1) ..................26-20 26.3 Description of Operation......................... 26-21 26.3.1 Setup of the A/D conversion channel ....................26-21 26.3.2 Operation of Successive Approximation Type A/D Converter ............
Page 16 32.3.2 The method of programming of Code-Option data ................32-4 Appendixes Appendix A Registers ............................A-1 Appendix B Package Dimensions: ML610Q174-xxxGAZWAAL ..............B-1 Package Dimensions: ML610Q174-xxxGAZWAX ................ B-2 Appendix C Electrical Characteristics ......................... C-1 Appendix D The example of an application circuit .................... D-1 Appendix E Check List ............................
Page 17: Overview
Chapter 1 Overview...
Page 18: Features
ML610Q174 User’s Manual Chapter 1 Overview Overview Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Battery level detect circuit, LCD driver, are incorporated around 8-bit CPU nX-U8/100.
Page 19 ML610Q174 User’s Manual Chapter 1 Overview • Synchronous serial port − 2ch − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − Half-duplex − TXD/RXD × 2 channels − Bit length, parity/no parity, odd parity/even parity, 1 stop bit /2 stop bits −...
Page 20: Feul610Q174
• Shipment − 80-pin QFP (QFP80-P-1420-0.80) − ML610Q174-xxxGAZWAAL (Blank name: ML610Q174-NNNGAZWAAL), xxx: ROM code number − ML610Q174-xxxGAZWAX (Blank name: ML610Q174-NNNGAZWAX), xxx: ROM code number Note: The ML610Q174-xxxGAZWAAL (Blank name: ML610Q174-NNNGAZWAAL) is discontined product. Also, the package dimensions are different each other. Refer to the ” PACKAGE DIMENSIONS” on the page B-1 and B-2.
Page 21: Configuration Of Functional Blocks
SEG0 to SEG7 Driver *2 Select I/O port or LCD driver SEG8 to SEG23 *3 Select I/O port or A/D converter input SEG32 to SEG39 *4 Select I/O port or Analog comparator input BIAS Figure 1-1 Block Diagram of ML610Q174 FEUL610Q174...
Page 22: Pins
ML610Q174 User’s Manual Chapter 1 Overview Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML610Q174 QFP Package 64pin 41pin 40pin 65pin PF0/SEG32/SIN0 P80/COM0 PF1/SEG33/SCK0 P81/COM1 PF2/SEG34/ RXD0/SOUT0 P82/COM2 PF3/SEG35/TXD0/PWM4/TXD1 P83/COM3 PF4/SEG36/SIN1/PWM4 P84/VL1 PF5/SEG37/SCK1/PWM5 P85/VL2 PF6/SEG38/RXD1/SOUT1/PWM6 PF7/SEG39/TXD1/TXD0 P36/LSCLK TEST0 RESET_N TEST1_N...
Page 23: List Of Pins
ML610Q174 User’s Manual Chapter 1 Overview 1.3.2 List of Pins Table 1-1 lists the pins. In the I/O column, “—” denotes a power supply pin (for primary functions only), “I” an input pin, “O” an output pin, and “I/O” an input/output pin.
Page 24: Feul610Q174
ML610Q174 User’s Manual Chapter 1 Overview Primary function Secondary function Tertiary function Fourthly function Description Description Description Description name name name name C data SSIO0 data    Input/output port SIN0 input/output input SSIO0 C clock synchronous  ...
Page 25: Feul610Q174
ML610Q174 User’s Manual Chapter 1 Overview Primary function Secondary function Tertiary function Fourthly function Description Description Description Description name name name name          SEG1 LCD segment pin     ...
Page 26: Pin Description
ML610Q174 User’s Manual Chapter 1 Overview 1.3.3 Pin Description Table 1-2 shows the pin description. In the I/O column, “—” denotes an input pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin. Table 1-2 Pin Description...
Page 27 ML610Q174 User’s Manual Chapter 1 Overview Primary/ Pin name Description Logic Secondary General-purpose input port P00 to P03 General-purpose input ports. Provided with a secondary function for each Primary Positive port. Cannot be used as ports if their secondary functions are used.
Page 28 ML610Q174 User’s Manual Chapter 1 Overview Primary/ Pin name Description Logic Secondary UART Secondary UART0 data output pin. Allocated to the secondary function of the P43 and TXD0 Positive PF3 pins and the fourthly function of the P53 and PF7 pins Fourthly UART0 data input pin.
Page 29 ML610Q174 User’s Manual Chapter 1 Overview Primary/ Pin name Description Logic Secondary External interrupt External maskable interrupt input pins. It is possible, for each bit, to specify Positive/ EXI0–EXI3 whether the interrupt is enabled and select the interrupt edge by software.
Page 30: Termination Of Unused Pins
ML610Q174 User’s Manual Chapter 1 Overview 1.3.4 Termination of Unused Pins Table 1-3 shows the recommended termination of unused pins. Table 1-3 Termination of Unused Pins Recommended pin termination RESET_N open TEST0 open TEST1_N open Connect to V open P00 to P03...
Page 31: Cpu And Memory Space
Chapter 2 CPU and Memory Space...
Page 32: Overview
ML610Q174 User’s Manual Chapter 2 CPU and Memory Space CPU and Memory Space Overview This LSI incorporates 8-bit CPU nX-U8/100, and a LARGE model is selected for the memory model. For details of the CPU nX-U8/100, refer to the “nX-U8/100 Core Instruction Manual”.
Page 33: Data Memory Space
ML610Q174 User’s Manual Chapter 2 CPU and Memory Space Data Memory Space The data memory space of this LSI consists of the ROM window area, 4-Kbyte RAM area, SFR area, and the ROM reference area of Segment 1, the FLASH data area of Segment 2, and the ROM reference area of Segment 8 to Segment The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits as addressing specified by instructions.
Page 34: Instruction Length
ML610Q174 User’s Manual Chapter 2 CPU and Memory Space Instruction Length One instruction has a length of 16 bits. Data Type The two data types of byte (8 bits) and word (16 bits) are supported. FEUL610Q174-01...
Page 35: Description Of Registers
ML610Q174 User’s Manual Chapter 2 CPU and Memory Space Description of Registers 2.6.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value ⎯ 0F000H Data segment register FEUL610Q174-01...
Page 36: Data Segment Register (Dsr)
ML610Q174 User’s Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ DSR3 DSR2 DSR1 DSR0 Initial value DSR is a special function register (SFR) used to retain a data segment. For details of DSR, refer to the “nX-U8/100 Core Instruction Manual”.
Page 37: Reset Function
Chapter 3 Reset Function...
Page 38: Overview
ML610Q174 User’s Manual Chapter 3 Reset Function Reset Function 3.1 Overview This LSI has the four reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...
Page 39: Description Of Registers
ML610Q174 User’s Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value － ― 0F001H Reset status register RSTAT 3.2.2 Reset Status Register (RSTAT) Address：0F001H Access：R/W Access size：8 bits Initial value：Undefined...
Page 40: Description Of Operation
ML610Q174 User’s Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of the following causes.
Page 41: Mcu Control Function
Chapter 4 MCU Control Function...
Page 42: Overview
ML610Q174 User’s Manual Chapter 4 MCU Control Function MCU Control Function Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: (1) System reset mode (2) Program run mode (3) HALT mode (4) STOP mode For system reset mode, see Chapter 3, “Reset Function”.
Page 43: Description Of Registers
ML610Q174 User’s Manual Chapter 4 MCU Control Function Description of Registers 4.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value ⎯ ⎯ 0F008H Stop code acceptor STPACP ⎯ 0F009H Standby control register SBYCON ⎯ 0F028H Block control register 0 BLKCON0 ⎯...
Page 44: Stop Code Acceptor (Stpacp)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: − (Undefined) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ STPACP ⎯ ⎯ ⎯ ⎯ ⎯ ⎯...
Page 45: Standby Control Register (Sbycon)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SBYCON Initial value SBYCON is a special function register (SFR) to control operating mode of MCU.
Page 46: Block Control Register 0 (Blkcon0)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0 (BLKCON0) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BLKCON0 DTM1 DTM0 Initial value BLKCON0 is a special function register (SFR) that controls the operation of the relevant block.
Page 47: Block Control Register 2 (Blkcon2)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 2 (BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ BLKCON2 DI2C0 DUA1 DUA0 DSIO1 DSIO0 Initial value BLKCON2 is a special function register (SFR) that controls the operation of the relevant block.
Page 48 ML610Q174 User’s Manual Chapter 4 MCU Control Function Note: • If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be invalid, an initial value is read when a register is read.
Page 49: Block Control Register 4 (Blkcon4)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 4 (BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ BLKCON4 DLCD DBLD DSAD Initial value BLKCON4 is a special function register (SFR) that controls the operation of the relevant block.
Page 50: Block Control Register 6 (Blkcon6)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 6 (BLKCON6) Address: 0F02EH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ BLKCON6 DTMB DTMA DTM9 DTM8 Initial value BLKCON6 is a special function register (SFR) that controls the operation of the relevant block.
Page 51: Block Control Register 7 (Blkcon7)
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.2.8 Block Control Register 7 (BLKCON7) Address: 0F02FH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ BLKCON7 DPW6 DPW５ DPW4 Initial value BLKCON7 is a special function register (SFR) that controls the operation of the relevant block.
Page 52: Description Of Operation
ML610Q174 User’s Manual Chapter 4 MCU Control Function Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, WDT overflow reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.
Page 53: Stop Mode
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value) to the stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”,...
Page 54 ML610Q174 User’s Manual Chapter 4 MCU Control Function When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and high-speed oscillation and low-speed oscillation stop.
Page 55: Note On Return Operation From Stop/Halt Mode
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
Page 56: Block Control Function
ML610Q174 User’s Manual Chapter 4 MCU Control Function 4.3.4 Block control function To use this block control function, supply current can be reduced more, by stopping completely operation of the unused function. The initial value of each bit of each block control register is "0", and operation of each block is enabled. If the appropriate bit is set to “1”...
Page 57: Interrupts (Ints)
Chapter 5 Interrupts (INTs)
Page 58: Overview
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) Interrupts (INTs) Overview This LSI has 27 interrupt sources (External interrupts: 4 sources, Internal interrupts: 23 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 6, “Clock Generation Circuit”...
Page 59: Description Of Registers
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F010H Interrupt enable register 0 ⎯ 0F011H Interrupt enable register 1 ⎯ 0F012H Interrupt enable register 2 ⎯...
Page 60: Interrupt Enable Register 0 (Ie0)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.2 Interrupt Enable Register 0 (IE0) Address: 0F010H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ELOSC Initial value IE0 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 61: Interrupt Enable Register 1 (Ie1)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.3 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ EP03 EP02 EP01 EP00 Initial value IE1 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 62: Interrupt Enable Register 2 (Ie2)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.4 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ EI2C0 ESAD ESIO1 ESIO0 Initial value IE2 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 63: Interrupt Enable Register 3 (Ie3)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.5 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ETM9 ETM8 ETM1 ETM0 Initial value IE3 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 64: Interrupt Enable Register 4 (Ie4)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.6 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ECMP1 ECMP0 EUA1 EUA0 Initial value IE4 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 65: Interrupt Enable Register 5 (Ie5)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.7 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ETMB ETMA Initial value IE5 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 66: Interrupt Enable Register 6 (Ie6)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.8 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ EL32H EL128H EPW6 EPW5 EPW4 Initial value IE6 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 67: Interrupt Enable Register 7 (Ie7)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.9 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ E16H Initial value IE7 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 68: Interrupt Request Register 0 (Irq0)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.10 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IRQ0 QLOSC QWDT Initial value IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 69: Interrupt Request Register 1 (Irq1)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.11 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ IRQ1 QP03 QP02 QP01 QP00 Initial value IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 70: Interrupt Request Register 2 (Irq2)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.12 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ IRQ2 QI2C0 QSAD QSIO1 QSIO0 Initial value IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 71: Interrupt Request Register 3 (Irq3)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.13 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ IRQ3 QTM9 QTM8 QTM1 QTM0 Initial value IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 72: Interrupt Request Register 4 (Irq4)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.14 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ IRQ4 QCMP1 QCMP0 QUA1 QUA0 Initial value IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 73: Interrupt Request Register 5 (Irq5)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.15 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IRQ5 QTMB QTMA Initial value IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 74: Interrupt Request Register 6 (Irq6)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.16 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ IRQ6 Q32H Q128H QPW6 QPW5 QPW4 Initial value IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 75 ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) • When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed.
Page 76: Interrupt Request Register 7 (Irq7)
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.2.17 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IRQ7 Q16H Initial value IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 77: Description Of Operation
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) Description of Operation With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 26 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7).
Page 78: Maskable Interrupt Processing
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination.
Page 79: Notes On Interrupt Routine
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.3.4 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
Page 80 ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack.
Page 81 ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) State B: Non-maskable interrupt is being processed B-1: When the interrupt processing is not executed in the interrupt routine. • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to PC and those of the EPSW register PSW.
Page 82: Interrupt Disable State
ML610Q174 User’s Manual Chapter 5 Interrupts (INTs) 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state.
Page 83: Clock Generation Circuit
Chapter 6 Clock Generation Circuit...
Page 84: Overview
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Clock Generation Circuit Overview The clock generation circuit generates and supplies a low-speed clock (LSCLK), high-speed clock (HSCLK), system clock (SYSCLK), and high-speed output clock (OUTCLK). LSCLK and HSCLK operate as the time-base clocks for peripheral circuits, SYSCLK as the basic operating clock of the CPU, and OUTCLK as the clock to be output from ports.
Page 85: List Of Pins
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin name Input/Output Description Pin for connecting a crystal for low-speed clock Pin for connecting a crystal for low-speed clock The crystal or the ceramic oscillator connecting pin for high-speed clocks P10/OSC0 Used for the secondary function of the P10 pin.
Page 86: Description Of Registers
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Description of Registers 6.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F002H Frequency control register 0 FCON0 8/16 FCON 0F003H Frequency control register 1 FCON1 ― 0F070H...
Page 87: Frequency Control Register 0(Fcon0)
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0(FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 3BH ⎯ ⎯ FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0 Initial value FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
Page 88 ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Note: − To switch the mode of the high-speed clock generation circuit using the OSCM1 and OSCM0 bits, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to “0”).
Page 89: Frequency Control Register 1 (Fcon1)
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 83H ⎯ ⎯ ⎯ ⎯ ⎯ FCON1 LPLL ENOSC SYSCLK Initial value FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
Page 90: Frequency Status Register (Fstat)
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.2.4 Frequency Status Register (FSTAT) Address: 0F070H Access: R/W Access size: 8 bits Initial value: 04H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ FCON1 LOSCS Initial value FSTAT is a special function register (SFR) to show the status of each oscillation.
Page 91: Description Of Operation
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit (32.768 crystal oscillation circuit) Figure 6-3 shows the configuration of the low-speed clock generation circuit. A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation...
Page 92: Operation Of The Low-Speed Clock Generation Circuit
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.3.1.3 Operation of the Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. After counting a built-in RC oscillation clock 128 times, a built-in RC oscillation clock is supplied to a circumference ) and circuit as a low-speed clock after powered on.
Page 93: High-Speed Clock
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock The high-speed clock generation circuit can choose built-in PLL (Phase Locked Loop) oscillation mode, crystal / ceramic oscillation mode, and a high-speed external clock input mode. 6.3.2.1 Built-in PLL Oscillation Mode The PLL oscillation circuit generates a clock of 16 MHz (= Low-speed clock ×...
Page 94: High-Speed External Clock Input Mode
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.3 High-Speed External Clock Input Mode In high-speed external clock input mode, an external clock is input from the P10/OSC0 pin. Figure 6-8 shows the circuit configuration in high-speed external clock input mode.
Page 95: Operation Of High-Speed Clock Generation Circuit
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.4 Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit starts with built-in PLL oscillation mode by reset generation at the time of the power supply injection. The LSI shifts to a system reset mode by reset generation at the time of the power on and shifts to a program operation mode after oscillation stabilization period (8192 counts) for high-speed clock, and a CPU starts operations.
Page 96 ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Figure 6-10 Operation of the High-Speed Clock Generation Circuit in Crystal/Ceramic Oscillation Mode FEUL610Q174-01 6-13...
Page 97: Switching Of System Clock
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-11 shows a flow of system clock switching processing (HSCLK→LSCLK) and Figure 6-12 shows a flow of system clock switching processing (LSCLK→HSCLK).
Page 98: Register Setup Of The Port
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit Register setup of the port For enable a clock output function, each related port register needs to be set up. Refer to the Chapter 16, “Port 2”, the Chapter 17, “Port 3” for details of each register.
Page 99: When The P20 Pin (Lsclk:output) Operates As The Low-Speed Clock Output Function
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.4.2 When the P20 pin (LSCLK:output) operates as the low-speed clock output function The low-speed clock output is selected as the secondary function of the P20 pin by setting P20MD bit (P2MOD register: bit0) to “1”.
Page 100: When The P36 Pin (Lsclk:output) Operates As The Low-Speed Clock Output Function
ML610Q174 User’s Manual Chapter 6 Clock Generation Circuit 6.4.3 When the P36 pin (LSCLK:output) operates as the low-speed clock output function The low-speed clock output is selected as the secondary function of the P36 pin by setting P36MD bit (P3MOD register: bit6) to “1”.
Page 101: Time Base Counter
Chapter 7 Time Base Counter...
Page 102: Overview
ML610Q174 User’s Manual Chapter 7 Time Base Counter Time Base Counter Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically.
Page 103 ML610Q174 User’s Manual Chapter 7 Time Base Counter HSCLK HTBDR HTBCLK (8.192MHz) 1/n-Counter 8.192MHz to 512Hz RESET (Internal signal) Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK is changed by setting of SYSC1 bit and SYSC0 bit in the frequency control register 0 (FCON0).
Page 104: Description Of Registers
ML610Q174 User’s Manual Chapter 7 Time Base Counter Description of Registers 7.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value ⎯ Low-speed time base counter register 0F00AH LTBR High-speed time base counter ⎯ 0F00BH HTBDR frequency divide register...
Page 105: Low-Speed Time Base Counter (Ltbr)
ML610Q174 User’s Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter.
Page 106: High-Speed Time Base Counter Divide Register (Htbdr)
ML610Q174 User’s Manual Chapter 7 Time Base Counter 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ HTBDR HTD3 HTD2 HTD1 HTD0 Initial value HTBDR is a special function register (SFR) to set the divide ratio of the 4-bit, 1/n counter.
Page 107: Low-Speed Time Base Counter Frequency Adjustment Registers L And H (Ltbadjl, Ltbadjh)
ML610Q174 User’s Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bits Initial value: 00H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1...
Page 108: Description Of Operation
ML610Q174 User’s Manual Chapter 7 Time Base Counter Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T1HZ outputs of LTBC are used as time base interrupts and an interrupt is requested on the falling edge of each output.
Page 109: High-Speed Time Base Counter
ML610Q174 User’s Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK.
Page 110: Low-Speed Time Base Counter Frequency Adjustment Function
ML610Q174 User’s Manual Chapter 7 Time Base Counter 7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers (LTBADJH and LTBADJL).
Page 111: Timers
Chapter 8 Timers...
Page 112: Overview
ML610Q174 User’s Manual Chapter 8 Timers Timers Overview This LSI has a 6-channels of 8-bit timers. For input clocks, see Chapter 6, “Clock Generation Circuit”. 8.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0,1,8 to B) and timer data register (TMnD) coincide.
Page 113 ML610Q174 User’s Manual Chapter 8 Timers TMnINT Match Write TMnC Comparator P22/TM9OUT P23/TMBOUT TMmNEG External clock LSCLK P46/T8ACK TMnCON0 TnCK HTBCLK TMnC TMnD P47/T9BCK TMnCON1 n=8～B Data bus m=9,B (c) 8-bit Timer Mode (Timers 8 to B) TMmINT TMmNEG P22/TM9OUT...
Page 114: Description Of Registers
ML610Q174 User’s Manual Chapter 8 Timers Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F030H Timer 0 data register TM0D 8/16 0FFH TM0DC 0F031H Timer 0 counter register TM0C 0F032H Timer 0 control register 0...
Page 115: Timer 0 Data Register (Tm0D)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.2 Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 0FFH TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value.
Page 116: Timer 1 Data Register (Tm1D)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.3 Timer 1 Data Register (TM1D) Address: 0F034H Access: R/W Access size: 8 bits Initial value: 0FFH TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C).
Page 117: Timer 8 Data Register (Tm8D)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.4 Timer 8 Data Register (TM8D) Address: 0F8E0H Access: R/W Access size: 8 bits Initial value: 0FFH TM8D T8D7 T8D6 T8D5 T8D4 T8D3 T8D2 T8D1 T8D0 Initial value TM8D is a special function register (SFR) to set the value to be compared with the value of the timer 8 counter register (TM8C).
Page 118: Timer 9 Data Register (Tm9D)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.5 Timer 9 Data Register (TM9D) Address: 0F8E4H Access: R/W Access size: 8 bits Initial value: 0FFH TM9D T9D7 T9D6 T9D5 T9D4 T9D3 T9D2 T9D1 T9D0 Initial value TM9D is a special function register (SFR) to set the value to be compared with the value of the timer 9 counter register (TM9C).
Page 119: Timer A Data Register (Tmad)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.6 Timer A Data Register (TMAD) Address: 0F8E8H Access: R/W Access size: 8 bits Initial value: 0FFH TMAD TAD7 TAD6 TAD5 TAD4 TAD3 TAD2 TAD1 TAD0 Initial value TMAD is a special function register (SFR) to set the value to be compared with the value of the timer A counter register (TMAC).
Page 120: Timer B Data Register (Tmbd)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.7 Timer B Data Register (TMBD) Address: 0F8ECH Access: R/W Access size: 8 bits Initial value: 0FFH TMBD TBD7 TBD6 TBD5 TBD4 TBD3 TBD2 TBD1 TBD0 Initial value TMBD is a special function register (SFR) to set the value to be compared with the value of the timer B counter register (TMBC).
Page 121: Timer 0 Counter Register (Tm0C)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.8 Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H TM0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 Initial value TM0C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 122: Timer 1 Counter Register (Tm1C)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.9 Timer 1 Counter Register (TM1C) Address: 0F035H Access: R/W Access size: 8 bits Initial value: 00H TM1C T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 Initial value TM1C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 123: Timer 8 Counter Register (Tm8C)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.10 Timer 8 Counter Register (TM8C) Address: 0F8E1H Access: R/W Access size: 8 bits Initial value: 00H TM8C T8C7 T8C6 T8C5 T8C4 T8C3 T8C2 T8C1 T8C0 Initial value TM8C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 124: Timer 9 Counter Register (Tm9C)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.11 Timer 9 Counter Register (TM9C) Address: 0F8E5H Access: R/W Access size: 8 bits Initial value: 00H TM9C T9C7 T9C6 T9C5 T9C4 T9C3 T9C2 T9C1 T9C0 Initial value TM9C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 125: Timer A Counter Register (Tmac)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.12 Timer A Counter Register (TMAC) Address: 0F8E9H Access: R/W Access size: 8 bits Initial value: 00H TMAC TAC7 TAC6 TAC5 TAC4 TAC3 TAC2 TAC1 TAC0 Initial value TMAC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 126: Timer B Counter Register (Tmbc)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.13 Timer B Counter Register (TMBC) Address: 0F8EDH Access: R/W Access size: 8 bits Initial value: 00H TMBC TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Initial value TMBC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 127: Timer 0 Control Register 0 (Tm0Con0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.14 Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ TM0CON0 T01M16 T0CS1 T0CS0 Initial value TM0CON0 is a special function register (SFR) to control timer 0.
Page 128: Timer 1 Control Register 0 (Tm1Con0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.15 Timer 1 Control Register 0 (TM1CON0) Address: 0F036H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TM1CON0 T1CS1 T1CS0 Initial value TM1CON0 is a special function register (SFR) to control timer 1.
Page 129: Timer 8 Control Register 0 (Tm8Con0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.16 Timer 8 Control Register 0 (TM8CON0) Address: 0F8E2H Access: R/W Access size: 8 bits Initial value: 00H ⎯ Τ89Μ16 ⎯ ⎯ ⎯ TM8CON0 T8OST T8CS1 T8CS0 Initial value TM8CON0 is a special function register (SFR) to control timer 8.
Page 130: Timer 9 Control Register 0 (Tm9Con0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.17 Timer 9 Control Register 0 (TM9CON0) Address: 0F8E6H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ TM9CON0 T9OST T9NEG T9CS1 T9CS0 Initial value TM9CON0 is a special function register (SFR) to control timer 9.
Page 131: Timer A Control Register 0 (Tmacon0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.18 Timer A Control Register 0 (TMACON0) Address: 0F8EAH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ TMACON0 TAOST TABM16 TACS1 TACS0 Initial value TMACON0 is a special function register (SFR) to control timer A.
Page 132: Timer B Control Register 0 (Tmbcon0)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.19 Timer B Control Register 0 (TMBCON0) Address: 0F8EEH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ TMBCON0 TBOST TBNEG TBCS1 TBCS0 Initial value TMBCON0 is a special function register (SFR) to control timer B.
Page 133: Timer 0 Control Register 1 (Tm0Con1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.20 Timer 0 Control Register 1 (TM0CON1) Address: 0F033H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TM0CON1 T0STAT T0RUN Initial value TM0CON1 is a special function register (SFR) to control a timer 0.
Page 134: Timer 1 Control Register 1 (Tm1Con1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.21 Timer 1 Control Register 1 (TM1CON1) Address: 0F037H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TM1CON1 T1STAT T1RUN Initial value TM1CON1 is a special function register (SFR) to control timer 1.
Page 135: Timer 8 Control Register 1 (Tm8Con1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.22 Timer 8 Control Register 1 (TM8CON1) Address: 0F8E3H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TM8CON1 T8STAT T8RUN Initial value TM8CON1 is a special function register (SFR) to control timer 8.
Page 136: Timer 9 Control Register 1 (Tm9Con1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.23 Timer 9 Control Register 1 (TM9CON1) Address: 0F8E7H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TM9CON1 T9STAT T9RUN Initial value TM9CON1 is a special function register (SFR) to control timer 9.
Page 137: Timer A Control Register 1 (Tmacon1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.24 Timer A Control Register 1 (TMACON1) Address: 0F8EBH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TMACON1 TASTAT TARUN Initial value TMACON1 is a special function register (SFR) to control timer A.
Page 138: Timer B Control Register 1 (Tmbcon1)
ML610Q174 User’s Manual Chapter 8 Timers 8.2.25 Timer B Control Register 1 (TMBCON1) Address: 0F8EFH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TMBCON1 TBSTAT TBRUN Initial value TMBCON1 is a special function register (SFR) to control timer B.
Page 139: Description Of Operation
ML610Q174 User’s Manual Chapter 8 Timers Description of Operation When the TnRUN bit of timer 0,1,8 to B control register 1 (TMnCON1) is set to “1”, the timer counter (TMnC) is set to an operating state (TnSTAT is set to “1”) on the first falling edge of the timer clock (TnCK) being selected by the Timer 0,1,8 to B control register 0 (TMnCON0).
Page 140 ML610Q174 User’s Manual Chapter 8 Timers TnCK TnRUN TnSTAT Write TMnC TMnC TMnD TMnINT (n = 8 to B) TMmOUT (m=9,B) Figure 8-3 One-shot timer mode Operation Timing Diagram of Timer 8 to B Note: When the count value of TMnC and the value of a timer 8 to B data register (TMnD) are in agreement, a TnRUN bit is cleared automatically.
Page 141: Watchdog Timer
Chapter 9 Watchdog Timer...
Page 142: Overview
ML610Q174 User’s Manual Chapter 9 Watchdog Timer Watchdog Timer Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state.
Page 143: Description Of Registers
ML610Q174 User’s Manual Chapter 9 Watchdog Timer Description of Registers 9.2.1 List of Registers Address Name Symbol（Byte） Symbol（Word） Size Initial value － 0F00EH Watchdog timer control register WDTCON － 0F00FH Watchdog timer mode register WDTMOD FEUL610Q174-01...
Page 144: Watchdog Timer Control Register (Wdtcon)
ML610Q174 User’s Manual Chapter 9 Watchdog Timer 9.2.2 Watchdog Timer Control Register（WDTCON） Address：0F00EH Access：W Access size：8 bits Initial value：00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to clear the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.
Page 145: Watchdog Timer Mode Register (Wdtmod)
ML610Q174 User’s Manual Chapter 9 Watchdog Timer 9.2.3 Watchdog Timer Mode Register（WDTMOD） Address：0F00FH Access：W Access size：8 bits Initial value：02H WDTMOD －－－－－－ WDT1 WDT0 Initial value WDTMOD is a special function register to set the overflow period of the watchdog timer.
Page 146: Description Of Operation
ML610Q174 User’s Manual Chapter 9 Watchdog Timer Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H"...
Page 147 ML610Q174 User’s Manual Chapter 9 Watchdog Timer Figure 9-2 shows an example of watchdog timer operation. Program Low-speed start Occurrence of oscillation start ① abnormality RESET ②WDTMOD WDTMOD setting System reset setting ③ ④ ⑥ ⑦ Data： WDTCON Write WDTP...
Page 148: Handling Example When You Do Not Want To Use The Watch Dog Timer
ML610Q174 User’s Manual Chapter 9 Watchdog Timer 9.3.1 Handling example when you do not want to use the watch dog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt occurs and then a system reset occurs.
Page 149: Pwm
Chapter 10...
Page 150: Overview
ML610Q174 User’s Manual Chapter 10 10. PWM 10.1 Overview This LSI includes three channels of 16-bit PWM (Pulse Width Modulation). The PWM4 output (PWM4) function is assigned to P34 (Port 3), P43 (Port 4), P20 (Port 2), PF3 (Port F) and PF4 (Port F) as the tertiary function.
Page 151: Configuration
ML610Q174 User’s Manual Chapter 10 10.1.2 Configuration Figure 10-1 shows the configuration of the PWM circuit. PnNEG P34/PWM4 PnFLG Write PWnCH P43/PWM4 PWnINT Write PWnCL Output control circuit P20/PWM4 Emergency EMGINT stop control circuit PF3/PWM4 Cycle Duty P00/PW45EV0 Port Matched...
Page 152 ML610Q174 User’s Manual Chapter 10 P47/PWM5 P35/PWM5 P21/PWM5 PF5/PWM5 PmNEG P43/PWM4 P34/PWM4 P20/PWM4 PF3/PWM4 PnNEG PF4/PWM4 PnFLG PWnINT PmFLG Write PWnCH Write PWnCL Output control circuit Output control circuit Emergency EMGINT stop control circuit P00/PW45EV0 Cycle delay delay Duty Port...
Page 153: List Of Pins
ML610Q174 User’s Manual Chapter 10 10.1.3 List of Pins Pin name Input/output Function P34/PWM4 PWM4 output pin. Used for the tertiary function of the P34 pin. P43/PWM4 PWM4 output pin. Used for the tertiary function of the P43 pin. P20/PWM4 PWM4 output pin.
Page 154: Pwm4 Period Registers (Pw4Pl, Pw4Ph)
ML610Q174 User’s Manual Chapter 10 10.2.2 PWM4 Period Registers (PW4PL, PW4PH) Address: 0F8A0H Access: R/W Access size: 8 bits Initial value: 0FFH PW4PL P4P7 P4P6 P4P5 P4P4 P4P3 P4P2 P4P1 P4P0 At reset Address: 0F8A1H Access: R/W Access size: 8 bits...
Page 155: Pwm4 Duty Registers (Pw4Dl, Pw4Dh)
ML610Q174 User’s Manual Chapter 10 10.2.3 PWM4 Duty Registers (PW4DL, PW4DH) PW4DL P4D7 P4D6 P4D5 P4D4 P4D3 P4D2 P4D1 P4D0 At reset Address: 0F8A2H Access: R/W Access size: 8 bits Initial value: 00H PW4DH P4D15 P4D14 P4D13 P4D12 P4D11 P4D10...
Page 156: Pwm4 Counter Registers (Pw4Ch, Pw4Cl)
ML610Q174 User’s Manual Chapter 10 10.2.4 PWM4 Counter Registers (PW4CH, PW4CL) PW4CL P4C7 P4C6 P4C5 P4C4 P4C3 P4C2 P4C1 P4C0 At reset Address: 0F8A4H Access: R/W Access size: 8 bits Initial value: 00H PW4CH P4C15 P4C14 P4C13 P4C12 P4C11 P4C10...
Page 157: Pwm4 Control Register 0 (Pw4Con0)
ML610Q174 User’s Manual Chapter 10 10.2.5 PWM4 Control Register 0 (PW4CON0) PW4CON0 P4CLIG P4STPS P4INI P4NEG P4IS1 P4IS0 P4CS1 P4CS0 At reset Address: 0F8A6H Access: R/W Access size: 8 bits Initial value: 00H PW4CON0 is a special function register (SFR) to control PWM.
Page 158 ML610Q174 User’s Manual Chapter 10 • P4STPSEL (bit 6) The P4STPSEL bit is used to select whether or not to set the PWM4 output level back to its initial level when the PWM4 output is paused by P4RUN="0". The initial value level is selected by P4INI and inverted when P4NEG="1".
Page 159: Pwm4 Control Register 1 (Pw4Con1)
ML610Q174 User’s Manual Chapter 10 10.2.6 PWM4 Control Register 1 (PW4CON1) — PW4CON1 P4STAT P4FLG P4RUN — — — — At reset Address: 0F8A7H Access: R/W Access size: 8 bits Initial value: 40H PW4CON1 is a special function register (SFR) to control PWM4.
Page 160: Pwm4 Control Register 2 (Pw4Con2)
ML610Q174 User’s Manual Chapter 10 10.2.7 PWM4 Control Register 2 (PW4CON2) PW4CON2 P45MD P4MD — P4TGSEL P4STM1 P4STM0 P4TGE1 P4TGE0 At reset Address: 0F8A8H Access: R/W Access size: 8 bits Initial value: 00H PW4CON1 is a special function register (SFR) to control PWM4.
Page 161 ML610Q174 User’s Manual Chapter 10 • P4MD (bit 6) The P4MD bit is used to select the one-shot mode or repeat mode for PWM4. When the P4MD bit is set to “1”, PWM4 operates in the one-shot mode. This setting is also applied to PWM5 in the cooperation mode (P45MD=1).
Page 162: Pwm4 Control Register 3 (Pw4Con3)
ML610Q174 User’s Manual Chapter 10 10.2.8 PWM4 Control Register 3 (PW4CON3) PW4CON3 P4SDST — — P4DTMD — — P4SDE1 P4SDE0 At reset Address: 0F8A9H Access: R/W Access size: 8 bits Initial value: 10H PW4CON1 is a special function register (SFR) to control PWM4.
Page 163: Pwm5 Period Registers (Pw5Pl, Pw5Ph)
ML610Q174 User’s Manual Chapter 10 10.2.9 PWM5 Period Registers (PW5PL, PW5PH) Address: 0F8B0H Access: R/W Access size: 8 bits Initial value: 0FFH PW5PL P5P7 P5P6 P5P5 P5P4 P5P3 P5P2 P5P1 P5P0 At reset Address: 0F8B1H Access: R/W Access size: 8 bits...
Page 164: Pwm5 Duty Registers (Pw5Dl, Pw5Dh)
ML610Q174 User’s Manual Chapter 10 10.2.10 PWM5 Duty Registers (PW5DL, PW5DH) PW5DL P5D7 P5D6 P5D5 P5D4 P5D3 P5D2 P5D1 P5D0 At reset Address: 0F8B2H Access: R/W Access size: 8 bits Initial value: 00H PW5DH P5D15 P5D14 P5D13 P5D12 P5D11 P5D10...
Page 165: Pwm5 Counter Registers (Pw5Ch, Pw5Cl)
ML610Q174 User’s Manual Chapter 10 10.2.11 PWM5 Counter Registers (PW5CH, PW5CL) PW5CL P5C7 P5C6 P5C5 P5C4 P5C3 P5C2 P5C1 P5C0 At reset Address: 0F8B4H Access: R/W Access size: 8 bits Initial value: 00H PW5CH P5C15 P5C14 P5C13 P5C12 P5C11 P5C10...
Page 166: Pwm5 Control Register 0 (Pw5Con0)
ML610Q174 User’s Manual Chapter 10 10.2.12 PWM5 Control Register 0 (PW5CON0) PW5CON0 P5STPS P5INI P5NEG P5IS1 P5IS0 P5CS1 P5CS0 P5CLIG At reset Address: 0F8B6H Access: R/W Access size: 8 bits Initial value: 00H PW5CON0 is a special function register (SFR) to control PWM5.
Page 167 ML610Q174 User’s Manual Chapter 10 • P5STPSEL (bit 6) The P5STPSEL bit is used to select whether or not to set the PWM5 output level back to its initial level when the PWM5 output is paused by P5RUN="0". The initial value level is selected by P5INI and inverted when P5NEG="1".
Page 168: Pwm5 Control Register 1 (Pw5Con1)
ML610Q174 User’s Manual Chapter 10 10.2.13 PWM5 Control Register 1 (PW5CON1) PW5CON1 P5STAT P5FLG — — — — P5RUN — At reset Address: 0F8B7H Access: R/W Access size: 8 bits Initial value: 40H PW5CON1 is a special function register (SFR) to control PWM5.
Page 169: Pwm5 Control Register 2 (Pw5Con2)
ML610Q174 User’s Manual Chapter 10 10.2.14 PWM5 Control Register 2 (PW5CON2) P5TGSE PW5CON2 P5MD — P5STM1 P5STM0 P5TGE1 P5TGE0 — At reset Address: 0F8B8H Access: R/W Access size: 8 bits Initial value: 00H PW5CON2 is a special function register (SFR) to control PWM5.
Page 170 ML610Q174 User’s Manual Chapter 10 • P5TGSEL (bit 4) The P5TGSEL bit is used to select the pin used as the external input control pin. In the cooperation mode (P45MD=1), this setting is invalid, and the P4TGSEL setting is applied.
Page 171: Pwm6 Period Registers (Pw6Pl, Pw6Ph)
ML610Q174 User’s Manual Chapter 10 10.2.15 PWM6 Period Registers (PW6PL, PW6PH) Address: 0F8C0H Access: R/W Access size: 8 bits Initial value: 0FFH PW6PL P6P7 P6P6 P6P5 P6P4 P6P3 P6P2 P6P1 P6P0 At reset Address: 0F8C1H Access: R/W Access size: 8 bits...
Page 172: Pwm6 Duty Registers (Pw6Dl, Pw6Dh)
ML610Q174 User’s Manual Chapter 10 10.2.16 PWM6 Duty Registers (PW6DL, PW6DH) PW6DL P6D7 P6D6 P6D5 P6D4 P6D3 P6D2 P6D1 P6D0 At reset Address: 0F8C2H Access: R/W Access size: 8 bits Initial value: 00H PW6DH P6D15 P6D14 P6D13 P6D12 P6D11 P6D10...
Page 173: Pwm6 Counter Registers (Pw6Ch, Pw6Cl)
ML610Q174 User’s Manual Chapter 10 10.2.17 PWM6 Counter Registers (PW6CH, PW6CL) PW6CL P6C7 P6C6 P6C5 P6C4 P6C3 P6C2 P6C1 P6C0 At reset Address: 0F8C4H Access: R/W Access size: 8 bits Initial value: 00H PW6CH P6C15 P6C14 P6C13 P6C12 P6C11 P6C10...
Page 174: Pwm6 Control Register 0 (Pw6Con0)
ML610Q174 User’s Manual Chapter 10 10.2.18 PWM6 Control Register 0 (PW6CON0) PW6CON0 P6CLIG P6STPS P6INI P6NEG P6IS1 P6IS0 P6CS1 P6CS0 At reset Address: 0F8C6H Access: R/W Access size: 8 bits Initial value: 00H PW6CON0 is a special function register (SFR) to control PWM.
Page 175 ML610Q174 User’s Manual Chapter 10 • P6STPSEL (bit 6) The P6STPSEL bit is used to select whether or not to set the PWM6 output level back to its initial level when the PWM6 output is paused by P6RUN="0". The initial value level is selected by P6INI and inverted when P6NEG="1".
Page 176: Pwm6 Control Register 1 (Pw6Con1)
ML610Q174 User’s Manual Chapter 10 10.2.19 PWM6 Control Register 1 (PW6CON1) — PW6CON1 P6STAT P6FLG P6RUN — — — — At reset Address: 0F8C7H Access: R/W Access size: 8 bits Initial value: 40H PW6CON1 is a special function register (SFR) to control PWM6.
Page 177: Pwm6 Control Register 2 (Pw6Con2)
ML610Q174 User’s Manual Chapter 10 10.2.20 PWM6 Control Register 2 (PW6CON2) PW6CON2 — P6MD — P6TGSEL P6STM1 P6STM0 P6TGE1 P6TGE0 At reset Address: 0F8C8H Access: R/W Access size: 8 bits Initial value: 00H PW6CON1 is a special function register (SFR) to control PWM6.
Page 178 ML610Q174 User’s Manual Chapter 10 • P6TGSEL (bit 4) The P6TGSEL bit is used to select the pin used as the hardware control pin. Description P6TGSEL External input start/external input clear control Uses the P01/PW6EV0 pin (initial value) Uses the P31/PW6EV1 pin •...
Page 179: Description Of Operation
ML610Q174 User’s Manual Chapter 10 10.3 Description of Operation PWM has the six different operation modes described below. For details of each operation mode, see Sections 10.3.1 to 10.3.6. Operation mode Description P45MD P4DTMD PnMD — In standalone mode PWM4 and PWM5 independently and repeatedly work.
Page 180 ML610Q174 User’s Manual Chapter 10 There are the following 11 modes for start/stop/clear control of PWM. For hardware control, the PnTGSEL bit allows selection of the external input for control from P00/PW45EV0, P30/PW45EV1, P01/PW6EV0 and P31/PW6EV1. For details of each operation mode, see Section 10.3.7.
Page 181 ML610Q174 User’s Manual Chapter 10 10.3.1 Repeat Mode with PWM4, PWM5 and PWM6 Standalone Mode (P45MD=“0”, PnMD=“0”) When the PnRUN bit of the PWMn control register 1 (PWnCON1) is set to “1”, the PWM counters (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that is selected by the PWMn control register 0 (PWnCON0) and increment the count value on the second falling edge.
Page 182 ML610Q174 User’s Manual Chapter 10 After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Subsequent PWM interrupt periods are constant.
Page 183 ML610Q174 User’s Manual Chapter 10 10.3.2 One-shot Mode with PWM4, PWM5 and PWM6 Standalone Mode (P45MD=“0”, PnMD=“1”) When the PnRUN bit of the PWMn control register 1 (PWnCON1) is set to “1”, the PWM counters (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that is selected by the PWMn control register 0 (PWnCON0) and increment the count value on the second falling edge.
Page 184 ML610Q174 User’s Manual Chapter 10 After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued.
Page 185: Repeat Mode With Pwm4 And Pwm5 Cooperation Mode (Dead Time Setting Is Not Used) (P45Md="1", P4Dtmd="0", P4Md="0")
ML610Q174 User’s Manual Chapter 10 10.3.3 Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Not Used) (P45MD=“1”, P4DTMD=“0”, P4MD=“0”) When the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”, the PWM counters (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK)
Page 186 ML610Q174 User’s Manual Chapter 10 The period of the PWM4 signal (T ), the first half duration of the duty (T ), the delay1 period (T ), and PWD1 delay2 period (T ) of the PWM5 signal are expressed by the following equations.
Page 187 ML610Q174 User’s Manual Chapter 10 After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Subsequent PWM interrupt periods are constant.
Page 188: One-Shot Mode With Pwm4 And Pwm5 Cooperation Mode (Dead Time Setting Is Not Used) (P45Md="1", P4Dtmd="0", P4Md="1")
ML610Q174 User’s Manual Chapter 10 10.3.4 One-shot Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Not Used) (P45MD=“1”, P4DTMD=“0”, P4MD=“1”) When the P0RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”, the PWM counters (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK)
Page 189 ML610Q174 User’s Manual Chapter 10 The period of the PWM4 signal (T ), the first half duration of the duty (T ), the delay1 period (T ), and PWD1 delay2 period (T ) of the PWM5 signal are expressed by the following equations.
Page 190 ML610Q174 User’s Manual Chapter 10 After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Subsequent PWM interrupt periods are constant.
Page 191: Repeat Mode With Pwm4 And Pwm5 Cooperation Mode (Dead Time Setting Is Used) (P45Md="1", P4Dtmd="1", P4Md="0")
ML610Q174 User’s Manual Chapter 10 10.3.5 Repeat Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used) (P45MD=“1”, P4DTMD=“1”, P4MD=“0”) When the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”, the PWM counters (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK)
Page 192 ML610Q174 User’s Manual Chapter 10 The period of the PWM4 signal (T ), the first half duration of the duty (T ), the dead time (T ), and delay2 period (T ) of the PWM5 signal are expressed by the following equations.
Page 193 ML610Q174 User’s Manual Chapter 10 After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Subsequent PWM interrupt periods are constant.
Page 194 ML610Q174 User’s Manual Chapter 10 Note: When the PWM4 output is assigned to P34 (Port 3) or P43 (Port 4) or P20(Port2) or PF3(PortF) or PF4(PortF) as the tertiary function or the PWM5 output (PWM5) is assigned to P35 (Port 3) or P47 (Port 4) or P21(Port2)
Page 195: One-Shot Mode With Pwm4 And Pwm5 Cooperation Mode (Dead Time Setting Is Used) (P45Md="1", P4Dtmd="1", P4Md="1")
ML610Q174 User’s Manual Chapter 10 10.3.6 One-shot Mode with PWM4 and PWM5 Cooperation Mode (Dead Time Setting Is Used) (P45MD=“1”, P4DTMD=“1”, P4MD=“1”) When the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”, the PWM counters (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK)
Page 196 ML610Q174 User’s Manual Chapter 10 The period of the PWM4 signal (T ), the first half duration of the duty (T ), the dead time (T ), and delay2 period (T ) of the PWM5 signal are expressed by the following equations.
Page 197 ML610Q174 User’s Manual Chapter 10 After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Subsequent PWM interrupt periods are constant.
Page 198 ML610Q174 User’s Manual Chapter 10 Note: When the PWM4 output is assigned to P34 (Port 3) or P43 (Port 4) or P20(Port2) or PF3(PortF) or PF4(PortF) as the tertiary function or the PWM5 output (PWM5) is assigned to P35 (Port 3) or P47 (Port 4) or P21(Port2)
Page 199: Software Start Mode
ML610Q174 User’s Manual Chapter 10 10.3.7 Start, Stop, and Clear Operations of PWM4, PWM5 and PWM6 by External Input Control Setting the PnSTM1 and PnSTM0 bits of the PWMn control register 2 (PWnCON2) enables the start/stop/clear control of the PWM counters (PWnCH and PWnCL) using the external input (P00/PW45EV0 or P30/PW45EV1 port) that is selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2).
Page 200 ML610Q174 User’s Manual Chapter 10 PnTGE1=0, PnTGE0=1 When "H" level start and "L" level stop & clear are selected PnRUN P00/PW45EV0 P30/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to...
Page 201 ML610Q174 User’s Manual Chapter 10 PnTGE1=1, PnTGE0=0 When "L" level start and "H" level stop & clear are selected PnRUN P00/PW45EV0 P30/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to...
Page 202: External Input Start Mode
ML610Q174 User’s Manual Chapter 10 10.3.7.3 External Input Start Mode With the setting of PnSTM1="1" and PnSTM0="0" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the edge of the external input (P00/PW45EV0 or P30/PW45EV1 or P01/PW6EV0 or P31/PW6EV1 pin) that is selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2).
Page 203 ML610Q174 User’s Manual Chapter 10 PnTGE1=1, PnTGE0=0 When falling-edge start and rising-edge stop & clear are selected PnRUN P00/PW45EV0 P30/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up PWnCH/L 0000...
Page 204: Software Start Or External Input Clear Mode
ML610Q174 User’s Manual Chapter 10 10.3.7.4 Software Start or External Input Clear Mode With the setting of PnSTM1="1" and PnSTM0="1" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the PnRUN bit. When there is no edge input on the external input (P00/PW45EV0 or P30/PW45EV1 or P01/PW6EV0 or P31/PW6EV1 pin) selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2), the counter operates in the same way as the software start.
Page 205 ML610Q174 User’s Manual Chapter 10 PnTGE1=1, PnTGE0=0 When rising-edge clear is selected PnRUN P00/PW45EV0 P30/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output...
Page 206 ML610Q174 User’s Manual Chapter 10 PnTGE1=1, PnTGE0=1 Both-edge clear selected PnRUN P00/PW45EV0 P30/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up Count up PWnCH/L Count up 0000 0000 0000 0000...
Page 207: Emergency Stop Operation
ML610Q174 User’s Manual Chapter 10 10.3.8 Emergency Stop Operation Setting the P4SDE1 and P4SDE0 bits of the PWM4 control register 3 (PW4CON3) enables the emergency stop function with the external input (P00/PW45EV0 or P30/PW45EV1 pin) that is selected by P4TGSEL. Note that the emergency stop function is valid only in the cooperation mode (P45MD=“1”).
Page 208 ML610Q174 User’s Manual Chapter 10 Emergency stop by P4SDE1=1, P4SDE0=1 (Both edges) P00/P45EV0 P30/P45EV1 PnRUN P4SDST PW4INT PnFLG PWnCH/L 0000 0000 Count up 0000 Count up 0000 Count up 0000 0000 stop & clear stop & clear Emergency Emergency The PnINI bit allows selection of...
Page 209: Specifying Port Registers
ML610Q174 User’s Manual Chapter 10 10.4 Specifying Port Registers To output the PWM waveform, the applicable bit of each related port register needs to be set. See Chapter 18, “Port 3” and Chapter 19, “Port 4” for details about the port registers.
Page 210: Functioning P43 Pin (Pwm4) As Pwm Output
ML610Q174 User’s Manual Chapter 10 10.4.2 Functioning P43 Pin (PWM4) as PWM Output Set the P43MD1 bit (bit 3 of P4MOD1 register) to "1" and the P43MD0 bit (bit 3 of P4MOD0 register) to "0" to specify PWM4 as the tertiary function of P43.
Page 211: Functioning P35 Pin (Pwm5) As Pwm Output
ML610Q174 User’s Manual Chapter 10 10.4.3 Functioning P35 Pin (PWM5) as PWM Output Set the P35MD1 bit (bit 5 of P3MOD1 register) to "1" and the P35MD0 bit (bit 5 of P3MOD0 register) to "0" to specify PWM5 as the tertiary function of P35.
Page 212: Functioning P47 Pin (Pwm5) As Pwm Output
ML610Q174 User’s Manual Chapter 10 10.4.4 Functioning P47 Pin (PWM5) as PWM Output Set the P47MD1 bit (bit 7 of P4MOD1 register) to "1" and the P47MD0 bit (bit 7 of P4MOD0 register) to "0" to specify PWM5 as the tertiary function of P47.
Page 213: Functioning P53 Pin (Pwm6) As Pwm Output
ML610Q174 User’s Manual Chapter 10 10.4.5 Functioning P53 Pin (PWM6) as PWM Output Set the P53MD1 bit (bit 3 of P5MOD1 register) to "1" and the P53MD0 bit (bit 3 of P5MOD0 register) to "0" to specify PWM6 as the tertiary function of P53.
Page 214: Synchronous Serial Port
Chapter 11 Synchronous Serial Port...
Page 215: Overview
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port Synchronous Serial Port 11.1 Overview This LSI includes two channels of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin.
Page 216 ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port SIO1INT PF5/SCK1 PF4/SIN1 Shift register PF6/SOUT1 8bits/16bits Transmit register Receive register SIO0TRH,L SIO0RCH,L LSCLK Control HSCLK circuit LSB/MSB control SIO1CON SIO1MOD0 SIO1MOD1 PF5/SCK1 SIO1BUFH, SIO1BUFL Data bus SIO1BUFL: Serial port transmit/receive buffer L...
Page 217: List Of Pins
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.1.3 List of Pins Pin name Description Receive data input. P40/SIN0 Used for the tertiary function of the P40 pin. Synchronous clock input/output. P41/SCK0 Used for the tertiary function of the P41 pin.
Page 218: Description Of Registers
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2 Description of Registers 11.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Serial port 0 transmit/receive 0F280H SIO0BUFL 8/16 buffer L SIO0BUF Serial port 0 transmit/receive 0F281H...
Page 219: Serial Port Transmit/Receive Buffers (Sio0Bufl, Sio0Bufh)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits /16 bits Initial value: 00H SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 Initial value Address: 0F281H...
Page 220: Serial Port Transmit/Receive Buffers (Sio1Bufl, Sio1Bufh)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.3 Serial Port Transmit/Receive Buffers (SIO1BUFL, SIO1BUFH) Address: 0F288H Access: R/W Access size: 8 bits /16 bits Initial value: 00H SIO1BUFL S1B7 S1B6 S1B5 S1B4 S1B3 S1B2 S1B1 S1B0 Initial value Address: 0F289H...
Page 221: Serial Port Control Register (Sio0Con)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.4 Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SIO0CON S0EN Initial value SIO0CON is a special function register (SFR) to control the synchronous serial port.
Page 222: Serial Port Control Register (Sio1Con)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.5 Serial Port Control Register (SIO1CON) Address: 0F28AH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SIO1CON S1EN Initial value SIO1CON is a special function register (SFR) to control the synchronous serial port.
Page 223: Serial Port Mode Register 0 (Sio0Mod0)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.6 Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ SIO0MOD0 S0LG S0MD1 S0MD0 S0DIR Initial value SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port.
Page 224: Serial Port Mode Register 0 (Sio1Mod0)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.7 Serial Port Mode Register 0 (SIO1MOD0) Address: 0F28CH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ SIO0MOD0 S1LG S1MD1 S1MD0 S1DIR Initial value SIO1MOD0 is a special function register (SFR) to set mode of the synchronous serial port.
Page 225: Serial Port Mode Register 1 (Sio0Mod1)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.8 Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ SIO0MOD1 S0NEG S0CKT S0CK3 S0CK2 S0CK1 S0CK0 Initial value SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port.
Page 226: Serial Port Mode Register 1 (Sio1Mod1)
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.2.9 Serial Port Mode Register 1 (SIO1MOD1) Address: 0F28DH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ SIO1MOD1 S1NEG S1CKT S1CK3 S1CK2 S1CK1 S1CK0 Initial value SIO1MOD1 is a special function register (SFR) to set mode of the synchronous serial port.
Page 227: Description Of Operation
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.3 Description of Operation 11.3.1 Transmit Operation When “1” is written to the SnMD1 bit and “0” is written to the SnMD0 bit of the serial mode register (SIOnMOD0), this LSI is set to a transmit mode.
Page 228: Receive Operation
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.3.2 Receive Operation When “0” is written to the SnMD1 bit and “1” is written to the SnMD0 bit of the serial mode register (SIOnMOD0), this LSI is set to a receive mode.
Page 229: Transmit/Receive Operation
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.3.3 Transmit/Receive Operation When “1” is written to the SnMD1 bit and “1” is written to the SnMD0 bit of the serial mode register (SIOnMOD0), this LSI is set to a transmit/receive mode.
Page 230: Register Setup Of The Port
ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.4 Register setup of the port For enable the SSIO function, each related port register needs to be set up. Refer to the Chapter 16, “Port 4” for details of each register.
Page 231 ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port SSIO is selected as the secondary function of P42, P41, and P40 by setting P42MD1-P40MD1 bit (P4MOD1 register: bit2-0) to “1” and setting P42MD0-P40MD0 bit (P4MOD0 register: bit2-0) to “0”. It is the same setup as the case of master mode.
Page 232 ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.4.3 When operating the SSIO function in master mode using PF2 pin (SOUT0:output), PF1 pin (SCK0:input/output), and PF0 pin (SIN0:input). SSIO is selected as the secondary function of PF2, PF1, and PF0 by setting PF2MD1-PF0MD1 bit (PFMOD1 register: bit2-0) to “1”...
Page 233 ML610Q174 User’s Manual Chapter 11 Synchronous Serial Port 11.4.4 When operating the SSIO function in master mode using PF6 pin (SOUT1:output), PF5 pin (SCK1:input/output), and PF4 pin (SIN1:input). SSIO is selected as the secondary function of PF6, PF5, and PF4 by setting PF6MD1-PF4MD1 bit (PFMOD1 register: bit6-4) to “1”...
Page 234: Uart
Chapter 12 UART...
Page 235: Overview
ML610Q174 User’s Manual Chapter 12 UART UART 12.1 Overview This LSI includes UART (Universal Asynchronous Receiver Transmitter) which is an asynchronous serial interface of half-duplex communication.（A full-duplex is also possible by using 2 channels.） For the input clock, see Chapter 6, “Clock Generation Circuit”.
Page 236: List Of Pins
ML610Q174 User’s Manual Chapter 12 UART 12.1.3 List of Pins Pin name Description UART0 data input pin P02 / RXD0 Used for the primary function of the P02 pin. UART0 data input pin P42 / RXD0 Used for the secondary / fourthly function of the P42 pin.
Page 237: Uart0 Transmit/Receive Buffer (Ua0Buf)
ML610Q174 User’s Manual Chapter 12 UART 12.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) to store the transmit/receive data of the UART.
Page 238: Uart0 Control Register (Ua0Con)
ML610Q174 User’s Manual Chapter 12 UART 12.2.4 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ UA0CON U0EN Initial value UA0CON is a special function register (SFR) to start/stop communication of the UART.
Page 239: Uart0 Mode Register 0 (Ua0Mod0)
ML610Q174 User’s Manual Chapter 12 UART 12.2.6 UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bits Initial value: 06H ⎯ ⎯ UA0MOD0 U0RSEL1 U0RSS U0RSEL U0CK1 U0CK0 U0IO Initial value UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART.
Page 240: Uart1 Mode Register 0 (Ua1Mod0)
ML610Q174 User’s Manual Chapter 12 UART 12.2.7 UART1 Mode Register 0 (UA1MOD0) Address: 0F29AH Access: R/W Access size: 8/16 bits Initial value: 06H ⎯ ⎯ UA1MOD0 U1RSEL1 U1RSS U1RSEL U1CK1 U1CK0 U1IO Initial value UA1MOD0 is a special function register (SFR) to set the transfer mode of the UART.
Page 241: Uart0 Mode Register 1 (Ua0Mod1)
ML610Q174 User’s Manual Chapter 12 UART 12.2.8 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ UA0MOD1 U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART.
Page 242 ML610Q174 User’s Manual Chapter 12 UART • U0NEG (bit 5) The U0NEG bit is used to select positive logic or negative logic in the communication of the UART. U0NEG Description Positive logic (initial value) Negative logic • U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART.
Page 243: Uart1 Mode Register 1 (Ua1Mod1)
ML610Q174 User’s Manual Chapter 12 UART 12.2.9 UART1 Mode Register 1 (UA1MOD1) Address: 0F29BH Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ UA1MOD1 U1DIR U1NEG U1STP U1PT1 U1PT0 U1LG1 U1LG0 Initial value UA1MOD1 is a special function register (SFR) to set the transfer mode of the UART.
Page 244 ML610Q174 User’s Manual Chapter 12 UART • U1NEG (bit 5) The U1NEG bit is used to select positive logic or negative logic in the communication of the UART. U1NEG Description Positive logic (initial value) Negative logic • U1DIR (bit 6) The U1DIR bit is used to select LSB first or MSB first in the communication of the UART.
Page 245: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)
ML610Q174 User’s Manual Chapter 12 UART 12.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bits Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F295H Access: R/W...
Page 246: Uart1 Baud Rate Registers L, H (Ua1Brtl, Ua1Brth)
ML610Q174 User’s Manual Chapter 12 UART 12.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) Address: 0F29CH Access: R/W Access size: 8/16 bits Initial value: 0FFH UA1BRTL U1BR7 U1BR6 U1BR5 U1BR4 U1BR3 U1BR2 U1BR1 U1BR0 Initial value Address: 0F29DH Access: R/W...
Page 247: Uart0 Status Register (Ua0Stat)
ML610Q174 User’s Manual Chapter 12 UART 12.2.12 UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ UA0STAT U0FUL U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART.
Page 248 ML610Q174 User’s Manual Chapter 12 UART • U0FUL (bit 3) The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When transmit data is written in UA0BUF in transmit mode, this bit is set to “1” and when transmit data is transferred to the shift register, this bit is set to “0”.
Page 249: Uart1 Status Register (Ua1Stat)
ML610Q174 User’s Manual Chapter 12 UART 12.2.13 UART1 Status Register (UA1STAT) Address: 0F29EH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ UA1STAT U1FUL U1PER U1OER U1FER Initial value UA1STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART.
Page 250 ML610Q174 User’s Manual Chapter 12 UART • U1FUL (bit 3) The U1FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When transmit data is written in UA1BUF in transmit mode, this bit is set to “1” and when transmit data is transferred to the shift register, this bit is set to “0”.
Page 251: Description Of Operation
ML610Q174 User’s Manual Chapter 12 UART 12.3 Description of Operation 12.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.
Page 252: Baud Rate
ML610Q174 User’s Manual Chapter 12 UART 12.3.2 Baud Rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (UnCK1, UnCK0) of the UARTn mode register 0 (UAnMOD0). The count value of the baud rate generator can be set by writing it in the UARTn baud rate register H or L (UAnBRTH, UAnBRTL).
Page 253: Transmit Data Direction
ML610Q174 User’s Manual Chapter 12 UART 12.3.3 Transmit Data Direction Figure 12-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. Data length: 8 bits LSB transmission LSB reception U0B7 U0B6 U0B5 U0B3 U0B2 U0B0 U0B4 U0B1 MSB transmission...
Page 254: Transmit Operation
ML610Q174 User’s Manual Chapter 12 UART 12.3.4 Transmit Operation Transmission is started by setting the UnIO bit of the UARTn mode register 0 (UAnMOD0) to “0” to select transmit mode and setting the UnEN bit of the UARTn control register (UAnCON) to “1”.
Page 255 ML610Q174 User’s Manual Chapter 12 UART Figure 12-5 Operation Timing in Transmission FEUL610Q174-01 12-21...
Page 256: Receive Operation
ML610Q174 User’s Manual Chapter 12 UART 12.3.5 Receive Operation Reception is started by selecting a receive data input pin using the UnRSEL bit of the UARTn mode register 0 (UAnMOD0), then setting the UnIO bit of UAnMOD0 to “0” to select receive mode, and then setting the UnEN bit of the UARTn control register (UAnCON) to “1”.
Page 257 ML610Q174 User’s Manual Chapter 12 UART Figure 12-6 Operation Timing in Reception FEUL610Q174-01 12-23...
Page 258: Detection Of Start Bit
ML610Q174 User’s Manual Chapter 12 UART 12.3.5.1 Detection of Start bit The start bit is sampled by the baud rate generator clock (HSCLK). Therefore, there is a possibility that the start bit will be detected with a delay of a maximum of one cycle of the baud rate generator clock.
Page 259: Reception Margin
ML610Q174 User’s Manual Chapter 12 UART 12.3.5.3 Reception Margin If there are any errors between the baud rate on the transmitter side and the baud rate to be generated by the baud rate generator of the LSI, those errors will be accumulated until the last stop bit in one frame is shifted in, causing the reception margin to be reduced.
Page 260: Register Setup Of The Port
ML610Q174 User’s Manual Chapter 12 UART 12.4 Register setup of the port For operate the UART function, each related port register needs to be set up. Refer to the Chapter 17, “Port 5”, the Chapter 16, “Port 4” and the Chapter 13, “Port 0” for details of each register.
Page 261 ML610Q174 User’s Manual Chapter 12 UART 12.4.2 When operating the UART function using P43 pin (TXD0:output) and P02 pin (RXD0:input) The UART is selected as the secondary function of the P43 pin by setting P43MD1 bit (P4MOD1 register: bit3) to “0”...
Page 262 ML610Q174 User’s Manual Chapter 12 UART The P02 pin does not require input/output selection by the register, since it is only for an input. The setting value of P02C1 bit and P02C0 bit ($) is optional. Optional input modes are selected according to the state of the external circuit where the P02 pin is connected.
Page 263 ML610Q174 User’s Manual Chapter 12 UART 12.4.3 When operating the UART function using P53 pin (TXD1:output) and P52 pin (RXD1:input) The UART is selected as the secondary function of the P53 pin and the P52 pin by setting P53MD1-P52MD1 bit (P5MOD1 register: bit3-2) to “0”...
Page 264 ML610Q174 User’s Manual Chapter 12 UART 12.4.4 When operating the UART function using P53 pin (TXD1:output) and P03 pin (RXD1:input) The UART is selected as the secondary function of the P53 pin by setting P53MD0 bit (P5MOD0 register: bit3) to “0”...
Page 265 ML610Q174 User’s Manual Chapter 12 UART The P03 pin does not require input/output selection by the register, since it is only for an input. The setting value of P03C1 bit and P03C0 bit ($) is optional. Optional input modes are selected according to the state of the external circuit where the P03 pin is connected.
Page 266 ML610Q174 User’s Manual Chapter 12 UART 12.4.5 When operating the UART function using P53 pin (TXD0:output) and P42 pin (RXD0:input) The UART is selected as the fourthly function of the P53 pin by setting P53MD1 bit (P5MOD1 register: bit3) to “1”...
Page 267 ML610Q174 User’s Manual Chapter 12 UART The UART is selected as the fourthly function of the P42 pin by setting P42MD1 bit (P4MOD1 register: bit2, ) to “0” and setting P42MD0 bit (P4MOD0 register: bit2) to “1” register P4MOD1 register (Address:0F225H)
Page 268 ML610Q174 User’s Manual Chapter 12 UART 12.4.6 When operating the UART function using P43 pin (TXD1:output) and P52 pin (RXD1:input) The UART is selected as the fourthly function of the P43 pin by setting P43MD1 bit (P4MOD1 register: bit3) to “1”...
Page 269 ML610Q174 User’s Manual Chapter 12 UART The UART is selected as the fourthly function of the P52 pin by setting P52MD1 bit (P5MOD1 register: bit2, ) to “0” and setting P52MD0 bit (P5MOD0 register: bit2) to “1” register P5MOD1 register (Address:0F22DH)
Page 270: When Operating The Uart Function Using Pf3 Pin (Txd0:Output) And Pf2 Pin (Rxd0:Input)
ML610Q174 User’s Manual Chapter 12 UART 12.4.7 When operating the UART function using PF3 pin (TXD0:output) and PF2 pin (RXD0:input) The UART is selected as the secondary function of the PF3 pin and the PF2 pin by setting PF3MD1-PF2MD1 bit (PFMOD1 register: bit3-2) to “0”...
Page 271: When Operating The Uart Function Using Pf7 Pin (Txd1:Output) And Pf6 Pin (Rxd1:Input)
ML610Q174 User’s Manual Chapter 12 UART 12.4.8 When operating the UART function using PF7 pin (TXD1:output) and PF6 pin (RXD1:input) The UART is selected as the secondary function of the PF7 pin and the PF6 pin by setting PF7MD1-PF6MD1 bit (PFMOD1 register: bit7-6) to “0”...
Page 272: I 2 C Bus Interface
Chapter 13 C Bus Interface...
Page 273: Overview
ML610Q174 User’s Manual Chapter 13 C Bus Interface I2C Bus Interface 13.1 Overview This LSI includes 1 channel of I C bus interface (master). The secondary functions of Port 4 are assigned to the I C bus interface data input/output pin and the I C bus interface clock input/output pin.
Page 274: Description Of Registers
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2 Description of Registers 13.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2A0H C bus 0 receive register I2C0RD — 0F2A1H C bus 0 slave address register I2C0SA —...
Page 275: I 2 C Bus 0 Receive Register (I2C0Rd)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.2 C Bus 0 Receive Register (I2C0RD) Address: 0F2A0H Access: R Access size: 8 bits Initial value: 00H I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 Initial value I2C0RD is a read-only special function register (SFR) to store receive data.
Page 276: I 2 C Bus 0 Slave Address Register (I2C0Sa)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.3 C Bus 0 Slave Address Register (I2C0SA) Address: 0F2A1H Access: R/W Access size: 8 bits Initial value: 00H I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW Initial value I2C0SA is a special function register (SFR) to set the address and the transmit/receive mode of the slave device.
Page 277: I 2 C Bus 0 Transmit Data Register (I2C0Td)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.4 C Bus 0 Transmit Data Register (I2C0TD) Address: 0F2A2H Access: R/W Access size: 8 bits Initial value: 00H I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 Initial value I2C0TD is a special function register (SFR) to set transmit data.
Page 278: I 2 C Bus 0 Control Register (I2C0Con)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.5 C Bus 0 Control Register (I2C0CON) Address: 0F2A3H Access: R/W Access size: 8 bits Initial value: 00H I2C0CON I20ACT — — — — I20RS I20SP I20ST Initial value I2C0CON is a special function register (SFR) to control transmit and receive operations.
Page 279: I 2 C Bus 0 Mode Register (I2C0Mod)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.6 C Bus 0 Mode Register (I2C0MOD) Address: 0F2A4H Access: R/W Access size: 8 bits Initial value: 00H I2C0MOD — — — I20SYN I20DW1 I20DW0 I20MD I20EN Initial value I2C0MOD is a special function register (SFR) to set operating mode.
Page 280: I 2 C Bus 0 Status Register (I2C0Stat)
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.2.7 C Bus 0 Status Register (I2C0STAT) Address: 0F2A5H Access: R/W Access size: 8 bits Initial value: 00H I2C0STAT — — — — — I20ER I20ACR I20BB Initial value: I2C0STAT is a read-only special function register (SFR) to indicate the state of the I C bus interface.
Page 281: Description Of Operation
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.3 Description of Operation 13.3.1 Communication Operating Mode Communication is started when communication mode is selected by using the I C bus 0 mode register (I2C0MOD), the C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I bus 0 slave address register, and “1”...
Page 282: Communication Operation Timing
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.3.2 Communication Operation Timing Figures 13-2 to 13-4 show the operation timing and control method for each communication mode. Transmission Reception Start Stop Repeated start Reception of Transmission of Transmission of condition...
Page 283 ML610Q174 User’s Manual Chapter 13 C Bus Interface Figure 13-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledgment error Register I2C0SA=”xxxxxxx0B” setting I2C0CON=”01H” I2C0CON=”02H” Value of I2C0SA I2C0INT I20ST I2C0RD Value of I2C0SA I20ACR Figure 13-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide (transmit failure due to arbitration when a multi-masters is used), the I20ER bit of the I2C bus 0 status register (I2C0STAT) is set to “1”...
Page 284: Operation Waveforms
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.3.3 Operation Waveforms Figure 13-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 13-1 shows the relationship between communication speeds and HSCLK clock counts. Start condition...
Page 285: Functioning P41(Scl) And P40(Sda) As The I2C
ML610Q174 User’s Manual Chapter 13 C Bus Interface 13.4 Specifying port registers To enable the I C function, the applicable bit of each related port register needs to be set. See Chapter 18, “Port 4” for detail about the port registers.
Page 286: Port 0
Chapter 14 Port 0...
Page 287: Overview
ML610Q174 User’s Manual Chapter 14 Port 0 Port 0 14.1 Overview This LSI includes Port 0 (P00 to P03) which is a 4-bit input port. 14.1.1 Features • All bits support a maskable interrupt function. • Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit.
Page 288: List Of Pins
ML610Q174 User’s Manual Chapter 14 Port 0 14.1.3 List of Pins Pin name Description P00/EXI0/ Input port, External 0 interrupt, PW45EV0 input PW45EV0 P00/EXI1/ Input port, External 1 interrupt, PW6EV0 input PW6EV0 P02/EXI2/RXD0 Input port, External 2 interrupt, UART0 data input (RXD0）...
Page 289 ML610Q174 User’s Manual Chapter 14 Port 0 14.2 Description of Registers 14.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Depends on ⎯ 0F204H Port 0 data register pin status 0F206H Port 0 control register 0...
Page 290: Port 0 Data Register (P0D)
ML610Q174 User’s Manual Chapter 14 Port 0 14.2.2 Port 0 Data Register (P0D) Address: 0F204H Access: R Access size: 8 bits Initial value: Depends on pin status ― ― ― ― P03D P02D P01D P00D Initial value P0D is a special function register (SFR) to only read the pin level of Port 0.
Page 291: Port 0 Control Registers 0, 1 (P0Con0, P0Con1)
ML610Q174 User’s Manual Chapter 14 Port 0 14.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F206H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― ― P0CON0 P03C0 P02C0 P01C0 P00C0 Initial value Address: 0F207H...
Page 292: External Interrupt Control Registers 0, 1 (Exicon0, Exicon1)
ML610Q174 User’s Manual Chapter 14 Port 0 14.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) Address: 0F020H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― EXICON0 P03E0 P02E0 P01E0 P00E0 Initial value Address: 0F021H...
Page 293: External Interrupt Control Register 2 (Exicon2)
ML610Q174 User’s Manual Chapter 14 Port 0 14.2.5 External Interrupt Control Register 2 (EXICON2) Address: 0F022H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― EXICON2 P03SM P02SM P01SM P00SM Initial value EXICON2 is a special function register (SFR) to select detection of signal edge for interrupts with or without sampling.
Page 294: Description Of Operation
ML610Q174 User’s Manual Chapter 14 Port 0 14.3 Description of Operation For each pin of Port 0, the setting of the Port 0 control registers 0 and 1 (P0CON0 and P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor.
Page 295 ML610Q174 User’s Manual Chapter 14 Port 0 When “rising-edge interrupt; with sampling” is selected, The input level of P0n pins are checked by a T16kHz negative going edge. An interrupt condition will be satisfied if an input level is "H" consecutive two times.
Page 296: Port 1
Chapter 15 Port 1...
Page 297: Overview
ML610Q174 User’s Manual Chapter 15 Port 1 Port 1 15.1 Overview This LSI incorporates a 2-bit input port, Port 1 (P10, P11). Port 1 can have a high-speed oscillation pin or an external clock input pin. When the port is used as an external clock input pin, the P11 pin functions as an input pin.
Page 298: Description Of Registers
ML610Q174 User’s Manual Chapter 15 Port 1 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F208H Port 1 data register Depends on pin status Port 1 control register 0 0F20AH...
Page 299: Port 1 Data Register (P1D)
ML610Q174 User’s Manual Chapter 15 Port 1 15.2.2 Port 1 Data Register (P1D) Address: 0F208H Access: R Access size: 8 bits Initial value: Depends on pin status ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P11D P10D Initial value P1D is a special function register (SFR) dedicated to read the input level of the Port 1 pin.
Page 300: Port 1 Control Registers 0,1 (P1Con0, P1Con1)
ML610Q174 User’s Manual Chapter 15 Port 1 15.2.3 Port 1 Control Registers 0,1 (P1CON0, P1CON1) Address: 0F20AH Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P1CON0 P11C0 P10C0 Initial value Address: 0F20BH Access: R/W...
Page 301: Description Of Operation
ML610Q174 User’s Manual Chapter 15 Port 1 15.3 Description of Operation 15.3.1 Input Port Function For each pin of Port 1, one of high-impedance input mode, input mode with a pull-down resistor, and input mode with a pull-up resistor can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1). At system reset, high-impedance input mode is selected as the initial state.
Page 302: Port 2
Chapter 16 Port 2...
Page 303: Overview
ML610Q174 User’s Manual Chapter 16 Port 2 Port 2 16.1 Overview This LSI incorporates Port 2 (P20–P23), a 4-bit port for output only. Port 2 can output low-speed clock (LSCLK), high-speed clock (OUTCLK), Timer 9 out (TM9OUT) or Timer B out (TMBOUT), PWM4 output (PWM4), PWM5 output (PWM5) as its secondary functions.
Page 304: Description Of Registers
ML610Q174 User’s Manual Chapter 16 Port 2 16.2 Description of Registers 16.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F210H Port 2 data register 0F212H Port 2 control register 0 P2CON0 8/16 P2CON 0F213H...
Page 305: Port 2 Data Register (P2D)
ML610Q174 User’s Manual Chapter 16 Port 2 16.2.2 Port 2 Data Register (P2D) Address: 0F210H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ P23D P22D P21D P20D Initial value P2D is a special function register (SFR) to set the output value of Port 2. The value of this register is output to Port 2.
Page 306: Port 2 Control Registers 0, 1 (P2Con0, P2Con1)
ML610Q174 User’s Manual Chapter 16 Port 2 16.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) Address: 0F212H Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ P2CON0 P23C0 P22C0 P21C0 P20C0 Initial value Address: 0F213H...
Page 307: Port 2 Mode Register (P2Mod)
ML610Q174 User’s Manual Chapter 16 Port 2 16.2.4 Port 2 Mode Register (P2MOD) Address: 0F214H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ P2MOD P23MD P22MD P21MD P20MD Initial value Address: 0F215H Access: R/W Access size: 8 bits Initial value: 00H ⎯...
Page 308 ML610Q174 User’s Manual Chapter 16 Port 2 • P21MD, P21MD1 (bit 1) The P21MD, P21MD1 bit are used to select the primary function or the secondary function of the P21 pin. P21MD1 P21MD Description General-purpose input/output, Direct LED Drive (initial value)
Page 309: Description Of Operation
ML610Q174 User’s Manual Chapter 16 Port 2 16.3 Description of Operation 16.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and P2CON1).
Page 310: Port 3
Chapter 17 Port 3...
Page 311: Overview
ML610Q174 User’s Manual Chapter 17 Port 3 Port 3 17.1 Overview This LSI includes Port 3 (P30 to P36), which is a 7-bit input/output port. Port 3 can output a PWM output (PWM4, PWM5) as tertiary functional mode. For PWM out put, refer to Chapter 10, “PWM”.
Page 312: List Of Pins
ML610Q174 User’s Manual Chapter 17 Port 3 17.1.3 List of Pins Secondary function Tertiary Pin name Primary function function P30/ Input/output port －－ SA-ADC input AIN0/ PW45EV1 input PW45EV1 P31/ Input/output port －－ AIN1/ SA-ADC input PW6EV1 PW6EV1 input...
Page 313: Description Of Registers
ML610Q174 User’s Manual Chapter 17 Port 3 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F218H Port 3 data register ⎯ 0F219H Port 3 direction register P3DIR 0F21AH Port 3 control register 0...
Page 314: Port 3 Data Register (P3D)
ML610Q174 User’s Manual Chapter 17 Port 3 17.2.2 Port 3 Data Register (P3D) Address: 0F218H Access: R/W Access size: 8 bits Initial value: 00H ― P36D P35D P34D P33D P32D P31D P30D Initial value P3D is a special function register (SFR) to set values to be output to, or to read the input levels of, the pins of Port 3.
Page 315: Port 3 Direction Register (P3Dir)
ML610Q174 User’s Manual Chapter 17 Port 3 17.2.3 Port 3 Direction Register (P3DIR) Address: 0F219H Access: R/W Access size: 8 bits Initial value: 00H ― P3DIR P36DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3.
Page 316: Port 3 Control Registers 0, 1 (P3Con0, P3Con1)
ML610Q174 User’s Manual Chapter 17 Port 3 17.2.4 Port 3 Control Registers 0, 1 (P3CON0, P3CON1) Address: 0F21AH Access: R/W Access size: 8/16 bits Initial value: 00H ― P3CON0 P36C0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Initial value Address: 0F21BH...
Page 317 ML610Q174 User’s Manual Chapter 17 Port 3 When output mode is selected When input mode is selected (P34DIR bit = “0”) (P34DIR bit = “1”) P34C1 P34C0 Description P34 pin: High-impedance output (initial P34 pin: High-impedance output (initial value) value)
Page 318: Port 3 Mode Registers 0, 1 (P3Mod0, P3Mod1)
ML610Q174 User’s Manual Chapter 17 Port 3 17.2.5 Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1) Address: 0F21CH Access: R/W Access size: 8/16 bits Initial value: 00H ― P3MOD0 P36MD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Initial value Address: 0F21DH...
Page 319 ML610Q174 User’s Manual Chapter 17 Port 3 • P33MD1, P33MD0 (bit 3) The P33MD1 and P33MD0 bits are used to select the primary , secondary function or tertiary function of the P33 pin. P33MD1 P33MD0 Description General-purpose input/output mode (initial value)
Page 320: Description Of Operation
ML610Q174 User’s Manual Chapter 17 Port 3 17.3 Description of Operation 17.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1).
Page 321 Chapter 18 Port 4...
Page 322: Overview
ML610Q174 User’s Manual Chapter 18 Port 4 Port 4 18.1 Overview This LSI includes Port 4 (P40 to P47) which is an 8-bit input/output port. Port 4 can have the PWM output, UART, synchronous serial port or I C bus interface functions as secondary, tertiary and fourthly functions.
Page 323: List Of Pins
ML610Q174 User’s Manual Chapter 18 Port 4 18.1.3 List of Pins Fourthly function Pin name Primary function Secondary function Tertiary function C bus data SSIO0 data ⎯ P40/SDA/SIN0 Input/output port input input SSIO0 C bus clock ⎯ P41/SCL/SCK0 Input/output port...
Page 324: Description Of Registers
ML610Q174 User’s Manual Chapter 18 Port 4 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F220H Port 4 data register ⎯ 0F221H Port 4 direction register P4DIR 0F222H Port 4 control register 0...
Page 325: Port 4 Data Register (P4D)
ML610Q174 User’s Manual Chapter 18 Port 4 18.2.2 Port 4 Data Register (P4D) Address: 0F220H Access: R/W Access size: 8 bits Initial value: 00H P47D P46D P45D P44D P43D P42D P41D P40D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.
Page 326: Port 4 Direction Register (P4Dir)
ML610Q174 User’s Manual Chapter 18 Port 4 18.2.3 Port 4 Direction Register (P4DIR) Address: 0F221H Access: R/W Access size: 8 bits Initial value: 00H P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4.
Page 327: Port 4 Control Registers 0, 1 (P4Con0, P4Con1)
ML610Q174 User’s Manual Chapter 18 Port 4 18.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) Address: 0F222H Access: R/W Access size: 8/16 bits Initial value: 00H P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Initial value Address: 0F223H...
Page 328 ML610Q174 User’s Manual Chapter 18 Port 4 When output mode is selected When input mode is selected Setting of P45 pin (P45DIR bit = “0”) (P45DIR bit = “1”) P45C1 P45C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 329: Port 4 Mode Registers 0, 1 (P4Mod0, P4Mod1)
ML610Q174 User’s Manual Chapter 18 Port 4 18.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F224H Access: R/W Access size: 8/16 bits Initial value: 00H P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Initial value Address: 0F225H...
Page 330 ML610Q174 User’s Manual Chapter 18 Port 4 • P44MD1, P44MD0 (bit 4) The P44MD1 and P44MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the P44 pin. P44MD1 P44MD0 Description General-purpose input/output (initial value) Prohibited...
Page 331 ML610Q174 User’s Manual Chapter 18 Port 4 Note: If any bit combination out of the above is set to “Prohibited” and the corresponding bit of the port 4 is specified to output mode (selected in port4 control register), status of corresponding pin is fixed, regardless the contents of Port4...
Page 332: Description Of Operation
ML610Q174 User’s Manual Chapter 18 Port 4 18.3 Description of Operation 18.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1).
Page 333 Chapter 19 Port 5...
Page 334: Port 5
ML610Q174 User’s Manual Chapter 19 Port5 Port 5 19.1 Overview This LSI includes Port 5 (P50 to P53) which is an 4-bit input/output port. 19.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode.
Page 335: List Of Pins
ML610Q174 User’s Manual Chapter 19 Port5 19.1.3 List of Pins Quaternary Pin name Primary function Secondary function Tertiary function function P50/ Input/output port SSIO1 data ⎯ ⎯ SIN1/ SA-ADC input input AIN8 P51/ SSIO1 Input/output port ⎯ ⎯ SCK1/ synchronous clock...
Page 336: Description Of Registers
ML610Q174 User’s Manual Chapter 19 Port5 19.2 Description of Registers 19.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F228H Port 5 data register ⎯ 0F229H Port 5 direction register P5DIR 0F22AH Port 5 control register 0...
Page 337: Port 5 Data Register (P5D)
ML610Q174 User’s Manual Chapter 19 Port5 19.2.2 Port 5 Data Register (P5D) Address: 0F228H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― P53D P52D P51D P50D Initial value P5D is a special function register (SFR) to set the value to be output to the Port 5 pin or to read the input level of the Port 5.
Page 338: Port 5 Direction Register (P5Dir)
ML610Q174 User’s Manual Chapter 19 Port5 19.2.3 Port 5 Direction Register (P5DIR) Address: 0F229H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― P5DIR P53DIR P52DIR P51DIR P50DIR Initial value P5DIR is a special function register (SFR) to select the input/output mode of Port 5.
Page 339: Port 5 Control Registers 0, 1 (P5Con0, P5Con1)
ML610Q174 User’s Manual Chapter 19 Port5 19.2.4 Port 5 Control Registers 0, 1 (P5CON0, P5CON1) Address: 0F22AH Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― ― P5CON0 P53C0 P52C0 P51C0 P50C0 Initial value Address: 0F22BH Access: R/W...
Page 340 ML610Q174 User’s Manual Chapter 19 Port5 When output mode is selected When input mode is selected Setting of P51 pin (P51DIR bit = “0”) (P51DIR bit = “1”) P51C1 P51C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 341: Port 5 Mode Registers 0, 1 (P5Mod0, P5Mod1)
ML610Q174 User’s Manual Chapter 19 Port5 19.2.5 Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1) Address: 0F22CH Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― ― P5MOD0 P53MD0 P52MD0 P51MD0 P50MD0 Initial value Address: 0F22DH Access: R/W...
Page 342 ML610Q174 User’s Manual Chapter 19 Port5 • P50MD1, P50MD0 (bit 0) The P50MD1 and P50MD0 bits are used to select the primary, secondary, tertiary, or fourthly function of the P50 pin. P50MD1 P50MD0 Description General-purpose input/output mode (initial value) Prohibited...
Page 343: Description Of Operation
ML610Q174 User’s Manual Chapter 19 Port5 19.3 Description of Operation 19.3.1 Input/Output Port Functions For each pin of Port 5, either output or input is selected by setting the Port 5 direction register (P5DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 5 control registers 0 and 1 (P5CON0 and P5CON1).
Page 344 Chapter 20 Port 8...
Page 345: Overview
ML610Q174 User’s Manual Chapter 20 Port8 Port 8 20.1 Overview This LSI includes Port 8 (P80 to P85) which is an 6-bit input/output port. P83 to P80 can be individually selected in a Common output pin or a I/O port function by LCD port common selection register (LSELC0).
Page 346: List Of Pins
ML610Q174 User’s Manual Chapter 20 Port8 20.1.3 List of Pins Pin name Primary function P80/ COM0 Input/output port, COM0 P81/ COM1 Input/output port, COM1 P82/ COM2 Input/output port, COM2 P83/ COM3 Input/output port, COM3 P84/ VL1 Input/output port, VL1 P85/ VL2...
Page 347: Description Of Registers
ML610Q174 User’s Manual Chapter 20 Port8 20.2 Description of Registers 20.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F240H Port 8 data register ⎯ 0F241H Port 8 direction register P8DIR 0F242H Port 8 control register 0...
Page 348 ML610Q174 User’s Manual Chapter 20 Port8 20.2.2 Port 8 Data Register (P8D) Address: 0F240H Access: R/W Access size: 8 bits Initial value: 00H ― ― P85D P84D P83D P82D P81D P80D Initial value P8D is a special function register (SFR) to set the value to be output to the Port ８ pin or to read the input level of the Port 8.
Page 349 ML610Q174 User’s Manual Chapter 20 Port8 20.2.3 Port 8 Direction Register (P8DIR) Address: 0F241H Access: R/W Access size: 8 bits Initial value: 00H ― ― P8DIR P85DIR P84DIR P83DIR P82DIR P81DIR P80DIR Initial value P8DIR is a special function register (SFR) to select the input/output mode of Port 8.
Page 350 ML610Q174 User’s Manual Chapter 20 Port8 20.2.4 Port 8 Control Registers 0, 1 (P8CON0, P8CON1) Address: 0F242H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― P8CON0 P85C0 P84C0 P83C0 P82C0 P81C0 P80C0 Initial value Address: 0F243H Access: R/W...
Page 351 ML610Q174 User’s Manual Chapter 20 Port8 When output mode is selected When input mode is selected Setting of P83 pin (P83DIR bit = “0”) (P83DIR bit = “1”) P83C1 P83C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 352 ML610Q174 User’s Manual Chapter 20 Port8 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 8, either output or input is selected by setting the Port 8 direction register (P8DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 8 control registers 0 and 1 (P8CON0 and P8CON1).
Page 353: Port 9
Chapter 21 Port 9...
Page 354: Overview
ML610Q174 User’s Manual Chapter 21 Port9 Port 9 21.1 Overview This LSI incorporates Port 9 (P90–P91), a 2-bit port for output only. 21.1.1 Features • Allows direct LED drive. • High-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output can be selected for each bit.
Page 355: Description Of Registers
ML610Q174 User’s Manual Chapter 21 Port9 21.2 Description of Registers 21.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F248H Port 9 data register 0F24AH Port 9 control register 0 P9CON0 8/16 P9CON 0F24BH Port 9 control register 1...
Page 356: Port 9 Data Register (P9D)
ML610Q174 User’s Manual Chapter 21 Port9 21.2.2 Port 9 Data Register (P9D) Address: 0F210H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P91D P90D Initial value P9D is a special function register (SFR) to set the output value of Port 9. The value of this register is output to Port 9.
Page 357: Port 9 Control Registers 0, 1 (P9Con0, P9Con1)
ML610Q174 User’s Manual Chapter 21 Port9 21.2.3 Port 9 control registers 0, 1 (P9CON0, P9CON1) Address: 0F212H Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P9CON0 P91C0 P90C0 Initial value Address: 0F213H Access: R/W...
Page 358: Description Of Operation
ML610Q174 User’s Manual Chapter 21 Port9 21.3 Description of Operation 21.3.1 Output Port Function For each pin of Port 9, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 9 control registers 0 and 1 (P9CON0 and P9CON1).
Page 359: Port C
Chapter 22 Port C...
Page 360: Overview
ML610Q174 User’s Manual Chapter 22 PortC 22. Port C 22.1 Overview This LSI includes Port C (PC0 to PC7), which is a 8-bit input/output port. Either an I/O Port or a segment driver output can be selected as a function of SEG8 to SEG15 by a LCD port segment selection register(LSELS1).
Page 361: List Of Pins
ML610Q174 User’s Manual Chapter 22 PortC 22.1.3 List of Pins Pin name Primary function Secondary function Input/output port SEG8 Input/output port SEG9 Input/output port SEG10 Input/output port SEG11 Input/output port SEG12 Input/output port SEG13 Input/output port SEG14 Input/output port SEG15...
Page 362: Description Of Registers
ML610Q174 User’s Manual Chapter 22 PortC 22.2 Description of Registers 22.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F260H Port C data register ⎯ 0F261H Port C direction register PCDIR 0F262H Port C control register 0...
Page 363: Port C Data Register (Pcd)
ML610Q174 User’s Manual Chapter 22 PortC 22.2.2 Port C data register (PCD) Address: 0F260H Access: R/W Access size: 8 bits Initial value: 00H PC7D PC6D PC5D PC4D PC3D PC2D PC1D PC0D Initial value PCD is a special function register (SFR) to set the value to be output to the Port C pin or to read the input level of the Port C.
Page 364: Port C Direction Register (Pcdir)
ML610Q174 User’s Manual Chapter 22 PortC 22.2.3 Port C Direction Register (PCDIR) Address: 0F261H Access: R/W Access size: 8 bits Initial value: 00H PCDIR PC7DIR PC6DIR PC5DIR PC4DIR PC3DIR PC2DIR PC1DIR PC0DIR Initial value PCDIR is a special function register (SFR) to select the input/output mode of Port C.
Page 365: Port C Control Registers 0, 1 (Pccon0, Pccon1)
ML610Q174 User’s Manual Chapter 22 PortC 22.2.4 Port C control registers 0, 1 (PCCON0, PCCON1) Address: 0F262H Access: R/W Access size: 8/16 bits Initial value: 00H PCCON0 PC7C0 PC6C0 PC5C0 PC4C0 PC3C0 PC2C0 PC1C0 PC0C0 Initial value Address: 0F263H Access: R/W...
Page 366 ML610Q174 User’s Manual Chapter 22 PortC When output mode is selected When input mode is selected (PC4DIR bit = “0”) (PC4DIR bit = “1”) PC4C1 PC4C0 Description PC4 pin: High-impedance output (initial value) PC4 pin: High-impedance input PC4 pin: P-channel open drain output...
Page 367: Description Of Operation
ML610Q174 User’s Manual Chapter 22 PortC 22.3 Description of Operation 22.3.1 Input/Output Port Functions For each pin of Port C, either output or input is selected by setting the Port C direction register (PCDIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port C control registers 0 and 1 (PCCON0 and PCCON1).
Page 368: Port D
Chapter 23 Port D...
Page 369: Overview
ML610Q174 User’s Manual Chapter 23 PortD 23. Port D 23.1 Overview This LSI includes Port D (PD0 to PD7), which is a 8-bit input/output port. Either an I/O Port or a segment driver output can be selected as a function of SEG16 to SEG23 by a LCD port segment selection register(LSELS2).
Page 370: List Of Pins
ML610Q174 User’s Manual Chapter 23 PortD 23.1.3 List of Pins Pin name Primary function Secondary function Input/output port SEG16 Input/output port SEG17 Input/output port SEG18 Input/output port SEG19 Input/output port SEG20 Input/output port SEG21 Input/output port SEG22 Input/output port SEG23...
Page 371: Description Of Registers
ML610Q174 User’s Manual Chapter 23 PortD 23.2 Description of Registers 23.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F268H Port D data register ⎯ 0F269H Port D direction register PDDIR 0F26AH Port D control register 0...
Page 372: Port D Data Register (Pdd)
ML610Q174 User’s Manual Chapter 23 PortD 23.2.2 Port D data register (PDD) Address: 0F268H Access: R/W Access size: 8 bits Initial value: 00H PD7D PD6D PD5D PD4D PD3D PD2D PD1D PD0D Initial value PDD is a special function register (SFR) to set the value to be output to the Port D pin or to read the input level of the Port D.
Page 373: Port D Direction Register (Pddir)
ML610Q174 User’s Manual Chapter 23 PortD 23.2.3 Port D Direction Register (PDDIR) Address: 0F269H Access: R/W Access size: 8 bits Initial value: 00H PDDIR PD7DIR PD6DIR PD5DIR PD4DIR PD3DIR PD2DIR PD1DIR PD0DIR Initial value PDDIR is a special function register (SFR) to select the input/output mode of Port D.
Page 374: Port D Control Registers 0, 1 (Pdcon0, Pdcon1)
ML610Q174 User’s Manual Chapter 23 PortD 23.2.4 Port D control registers 0, 1 (PDCON0, PDCON1) Address: 0F26AH Access: R/W Access size: 8/16 bits Initial value: 00H PDCON0 PD7C0 PD6C0 PD5C0 PD4C0 PD3C0 PD2C0 PD1C0 PD0C0 Initial value Address: 0F26BH Access: R/W...
Page 375 ML610Q174 User’s Manual Chapter 23 PortD When output mode is selected When input mode is selected (PD4DIR bit = “0”) (PD4DIR bit = “1”) PD4C1 PD4C0 Description PD4 pin: High-impedance output (initial value) PD4 pin: High-impedance input PD4 pin: P-channel open drain output...
Page 376: Description Of Operation
ML610Q174 User’s Manual Chapter 23 PortD 23.3 Description of Operation 23.3.1 Input/Output Port Functions For each pin of Port D, either output or input is selected by setting the Port D direction register (PDDIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port D control registers 0 and 1 (PDCON0 and PDCON1).
Page 377: Port F
Chapter 24 Port F...
Page 378: Overview
ML610Q174 User’s Manual Chapter 24 PortF 24. Port F 24.1 Overview This LSI includes Port F (PF0 to PF7), which is a 8-bit input/output port. Either an I/O Port or a segment driver output can be selected as a function of SEG32 to SEG39 by a LCD port segment selection register(LSELS4).
Page 379: List Of Pins
ML610Q174 User’s Manual Chapter 24 PortF 24.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Fourthly function Input/output port SSIO0 data ⎯ ⎯ SEG32 input SSIO0 Input/output port ⎯ ⎯ clock ynchronous SEG33 input/output Input/output port UART0 data SSIO0 data ⎯...
Page 380: Description Of Registers
ML610Q174 User’s Manual Chapter 24 PortF 24.2 Description of Registers 24.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ 0F278H Port F data register ⎯ 0F279H Port F direction register PFDIR 0F27AH Port F control register 0...
Page 381 ML610Q174 User’s Manual Chapter 24 PortF 24.2.2 Port F data register (PFD) Address: 0F278H Access: R/W Access size: 8 bits Initial value: 00H PF7D PF6D PF5D PF4D PF3D PF2D PF1D PF0D Initial value PFD is a special function register (SFR) to set the value to be output to the Port F pin or to read the input level of the Port F.
Page 382 ML610Q174 User’s Manual Chapter 24 PortF 24.2.3 Port F Direction Register (PFDIR) Address: 0F279H Access: R/W Access size: 8 bits Initial value: 00H PFDIR PF7DIR PF6DIR PF5DIR PF4DIR PF3DIR PF2DIR PF1DIR PF0DIR Initial value PFDIR is a special function register (SFR) to select the input/output mode of Port F.
Page 383 ML610Q174 User’s Manual Chapter 24 PortF 24.2.4 Port F control registers 0, 1 (PFCON0, PFCON1) Address: 0F27AH Access: R/W Access size: 8/16 bits Initial value: 00H PFCON0 PF7C0 PF6C0 PF5C0 PF4C0 PF3C0 PF2C0 PF1C0 PF0C0 Initial value Address: 0F27BH Access: R/W...
Page 384 ML610Q174 User’s Manual Chapter 24 PortF When output mode is selected When input mode is selected (PF4DIR bit = “0”) (PF4DIR bit = “1”) PF4C1 PF4C0 Description PF4 pin: High-impedance output (initial value) PF4 pin: High-impedance input PF4 pin: P-channel open drain output...
Page 385: Port F Mode Registers 0, 1 (Pfmod0, Pfmod1)
ML610Q174 User’s Manual Chapter 24 PortF 24.2.5 Port F Mode Registers 0, 1 (PFMOD0, PFMOD1) Address: 0F27CH Access: R/W Access size: 8/16 bits Initial value: 00H PFMOD0 PF7MD0 PF6MD0 PF5MD0 PF4MD0 PF3MD0 PF2MD0 PF1MD0 PF0MD0 Initial value Address: 0F27DH Access: R/W...
Page 386 ML610Q174 User’s Manual Chapter 24 PortF • PF4MD1, PF4MD0 (bit 4) The PF4MD1 and PF4MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PF4 pin. PF4MD1 PF4MD0 Description General-purpose input/output (initial value) Prohibited SSIO0 data input PWM4 output •...
Page 387: Description Of Operation
ML610Q174 User’s Manual Chapter 24 PortF 24.3 Description of Operation 24.3.1 Input/Output Port Functions For each pin of Port F, either output or input is selected by setting the Port F direction register (PFDIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port F control registers 0 and 1 (PFCON0 and PFCON1).
Page 388: Lcd Drivers
Chapter 25 LCD Drivers...
Page 389: Overview
ML610Q174 User’s Manual Chapter 25 LCD Drivers LCD Drivers 25.1 Overview This LSI includes LCD drivers that display the contents that are set in the display register. The LCD drivers handle the LCD display functions with three blocks. 1. Display registers 2.
Page 390: Features
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.1.1 Features The LCD drivers are applicable to various types of LCD panels. The features include: • 128 dots max. (32seg x 4com) • 1/1 to 1/4 duty • 1/2, 1/3bias • Frame frequency selectable (8 types) •...
Page 391: Configuration Of The Lcd Drive Voltage Control Circuit
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.1.3 Configuration of the LCD drive voltage control circuit The power supply for LCD drivers can choose external division resistance and built-in division resistance with a bias mode register (BIASMOD). When external division resistance is chosen, connect external partial pressure resistance to the power supply pin for LCD drivers (V ), and impress LCD driver drive voltage..
Page 392: List Of Pins
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.1.4 List of Pins Pin name Description ⎯ P84/V Power supply pin for LCD bias ⎯ P85/V Power supply pin for LCD bias ⎯ Power supply pin for LCD bias P80/COM0 LCD common pin...
Page 393 ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2 Description of Registers 25.2.1 List of Registers Symbol Address Name Symbol (Byte) Size Initial value (Word) ⎯ 0F0F0H Bias circuit control register BIASCON ⎯ 0F0F2H Display mode register 0 DSPMOD0 ⎯ 0F0F4H...
Page 394: Bias Circuit Control Register 0 (Biascon)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.2 Bias Circuit Control Register 0 (BIASCON) Address: 0F0F0H Access: R/W Access size: 8 bits Initial value: 30H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BIASCON BSEL1 BSEL0 Initial value BIASCON is a special function register (SFR) to control the bias generation circuit.
Page 395: Display Mode Register 0 (Dspmod0)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.3 Display Mode Register 0 (DSPMOD0) Address: 0F0F2H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ DSPMOD0 FRM2 FRM1 FRM0 DUTY1 DUTY0 Initial value DSPMOD0 is a special function register (SFR) to control the display mode of the LCD drivers.
Page 396: Display Control Register (Dspcon)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.4 Display Control Register (DSPCON) Address: 0F0F4H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DSPCON LMD1 LMD0 Initial value DSPCON is a special function register (SFR) to control the LCD drivers.
Page 397: Bias Circuit Mode Register 0 (Biasmod)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.5 Bias circuit Mode Register 0 (BIASMOD) Address: 0F0F5H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ BIASMOD BRESDT2 BRESDT1 BRESDT0 BRESSEL1 BRESSEL0 Initial value BIASMOD is a special function register (SFR) to control the power supply for the LCD drivers.
Page 398: Display Registers (Dspr00 To Dspr17, Dspr20 To Dspr27)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.6 Display Registers (DSPR00 to DSPR17, DSPR20 to DSPR27) Address: 0F100H to 0F117H, 0F120H to 0F127H, Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ DSPRxx Initial value DSPRxx (xx = 00 to 17, 20 to 27) are special function registers (SFRs) to store display data.
Page 399 ML610Q174 User’s Manual Chapter 25 LCD Drivers Table 25-2 Display Registers Symbol Address Segment bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DSPR00 0F100H SEG0 DSPR01 0F101H SEG1 DSPR02 0F102H SEG2 DSPR03 0F103H SEG3 DSPR04 0F104H SEG4 DSPR05 0F105H SEG5...
Page 400: Lcd Port Segment Selection Register 1 (Lsels1)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.7 LCD port segment selection register 1 (LSELS1) Address: 0F8F1H Access: R/W Access size: 8 bits Initial value: 00H LSELS14 LSELS13 LSELS12 LSELS11 LSELS10 LSELS09 LSELS08 LSELS1 LSELS15 Initial value LSELS1 is a Special function register which selects I/O Port (port C) or Segment driver output as a function of SEG8 to SEG15 port.
Page 401 ML610Q174 User’s Manual Chapter 25 LCD Drivers • LSELS10 (bits 2) LSELS10 is a bit which selects I/O Port (PC2) or Segment driver output (SEG10) as a function of SEG10. LSELS10 Description Use as an I/O Port (PC2) (initial value) Use as a segment driver output (SEG10) •...
Page 402: Lcd Port Segment Selection Register 2 (Lsels2)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.8 LCD port segment selection register 2 (LSELS2) Address: 0F8F2H Access: R/W Access size: 8 bits Initial value: 00H LSELS22 LSELS21 LSELS20 LSELS19 LSELS18 LSELS17 LSELS16 LSELS2 LSELS23 Initial value LSELS2 is a Special function register which selects I/O Port (port D) or Segment driver output as a function of SEG16 to SEG23 port.
Page 403 ML610Q174 User’s Manual Chapter 25 LCD Drivers • LSELS18 (bits 2) LSELS18 is a bit which selects I/O Port (PD2) or Segment driver output (SEG18) as a function of SEG18. LSELS18 Description Use as an I/O Port (PD2) (initial value) Use as a segment driver output (SEG18) •...
Page 404: Lcd Port Segment Selection Register 4 (Lsels4)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.9 LCD port segment selection register 4 (LSELS4) Address: 0F8F4H Access: R/W Access size: 8 bits Initial value: 00H LSELS38 LSELS37 LSELS36 LSELS35 LSELS34 LSELS33 LSELS32 LSELS4 LSELS39 Initial value LSELS4 is a Special function register which selects I/O Port (port F) or Segment driver output as a function of SEG39 to SEG32 port.
Page 405 ML610Q174 User’s Manual Chapter 25 LCD Drivers • LSELS34 (bits 2) LSELS34 is a bit which selects I/O Port (PF2) or Segment driver output (SEG34) as a function of SEG34. LSELS34 Description Use as an I/O Port (PF2) (initial value) Use as a segment driver output (SEG34) •...
Page 406: Lcd Port Common Selection Register 0 (Lselc0)
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.2.10 LCD port common selection register 0 (LSELC0) Address: 0F8FCH Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ LSELC03 LSELC02 LSELC01 LSELC00 LSELS4 Initial value LSELC0 is a Special function register which selects I/O Port (port 8) or Common driver output as a function of COM0 to COM3 port.
Page 407: Description Of Operation
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3 Description of Operation 25.3.1 Operation of LCD Drivers and Bias Generation Circuit Figure 25-4 shows the operation of the LCD drivers and the bias generation circuit. Reset RESET_N LMD1, LMD0 Common output...
Page 408: Display Register Segment Map
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.2 Display Registers Segment Map Figure 25-5 shows the display registers segment map. DSPR27[3] DSPR26[3] DSPR01[3] DSPR00[3] COM3 DSPR27[2] DSPR26[2] COM2 DSPR01[2] DSPR00[2] DSPR27 [1] DSPR26[1] COM1 DSPR01[1] DSPR00[1] DSPR27 [0] DSPR26[0] DSPR01[0]...
Page 409: Built-In Division Resistance For Lcd Drive Voltage Generation
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.3 Built-in division resistance for LCD drive voltage generation Low resistance (20kΩ) and high resistance (200kΩ) are built in, and the division resistance can change the connection Duty of low resistance (20kΩ) by BRESDT2-BRESDT0. Figure 25-6 shows the consumption current (Typ) which flows into built-in division resistance of the connection Duty of low resistance (20kΩ).
Page 410: Common Output Waveforms For 1/4 Duty And 1/3 Bias
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.4 Common Output Waveform for 1/4 duty and 1/3 bias Figure 25-6 shows the common output waveforms for 1/4 duty and 1/3 bias. Frame Frequency About 32Hz to about 256Hz COM0 COM1 COM2...
Page 411: Segment Output Waveform For 1/4 Duty And 1/3 Bias
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.5 Segment Output Waveform for 1/4 duty and 1/3 bias Figure 25-7 shows the segment output waveforms for 1/4 duty and 1/3 bias. Frame Frequency About 32Hz to about 256Hz Data SEGn Data...
Page 412: Common Output Waveforms For 1/4 Duty And 1/2 Bias
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.6 Common Output Waveform for 1/4 duty and 1/2 bias Figure 25-8 shows the segment output waveforms for 1/4 duty and 1/2 bias. Frame Frequency About 32Hz to about 256Hz COM0 COM1 COM2...
Page 413: Segment Output Waveform For 1/4 Duty And 1/2 Bias
ML610Q174 User’s Manual Chapter 25 LCD Drivers 25.3.7 Segment Output Waveform for 1/4 duty and 1/2 bias Figure 25-9 shows the segment output waveforms for 1/4 duty and 1/2 bias. Frame Frequency About 32Hz to about 256Hz data SEGn data...
Page 414: Successive Approximation Type A/D Converter (Sa-Adc)
Chapter 26 Successive Approximation Type A/D Converter...
Page 415: Overview
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) Successive Approximation Type A/D Converter (SA-ADC) 26.1 Overview This LSI has a built-in 12-channel successive approximation type A/D converter (SA-ADC). The SA-ADC operates only when the DSAD bit of the block control register 4 (BLKCON4) is “0”. When the DSAD bit is “1”, every function of the SA-ADC is in a reset state.
Page 416: List Of Pins
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.1.3 List of Pins Pin name Description ⎯ Positive power supply pin for the successive approximation type A/D converter ⎯ Negative power supply pin for the successive approximation type A/D converter ⎯...
Page 417: Description Of Registers
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2 Description of Registers 26.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2D0H SA-ADC result register 0L SADR0L 8/16 SADR0 0F2D1H SA-ADC result register 0H...
Page 418: Sa-Adc Result Register 0L (Sadr0L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F2D0H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR0L SAR03 SAR02 Initial value SADR0L is a special function register (SFR) used to store SA-ADC conversion results on channel 0.
Page 419: Sa-Adc Result Register 1L (Sadr1L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F2D2H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR1L SAR13 SAR12 Initial value SADR1L is a special function register (SFR) used to store SA-ADC conversion results on channel 1.
Page 420: Sa-Adc Result Register 2L (Sadr2L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.6 SA-ADC Result Register 2L (SADR2L) Address: 0F2D4H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR2L SAR23 SAR22 Initial value SADR2L is a special function register (SFR) used to store SA-ADC conversion results on channel 2.
Page 421: Sa-Adc Result Register 3L (Sadr3L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.8 SA-ADC Result Register 3L (SADR3L) Address: 0F2D6H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR3L SAR33 SAR32 Initial value SADR3L is a special function register (SFR) used to store SA-ADC conversion results on channel 3.
Page 422: Sa-Adc Result Register 4L (Sadr4L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.10 SA-ADC Result Register 4L (SADR4L) Address: 0F2D8H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR4L SAR43 SAR42 Initial value SADR4L is a special function register (SFR) used to store SA-ADC conversion results on channel 4.
Page 423: Sa-Adc Result Register 5L (Sadr5L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.12 SA-ADC Result Register 5L (SADR5L) Address: 0F2DAH Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR5L SAR53 SAR52 Initial value SADR5L is a special function register (SFR) used to store SA-ADC conversion results on channel 5.
Page 424: Sa-Adc Result Register 6L (Sadr6L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.14 SA-ADC Result Register 6L (SADR6L) Address: 0F2DCH Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR6L SAR63 SAR62 Initial value SADR6L is a special function register (SFR) used to store SA-ADC conversion results on channel 6.
Page 425: Sa-Adc Result Register 7L (Sadr7L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.16 SA-ADC Result Register 7L (SADR7L) Address: 0F2DEH Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR7L SAR73 SAR72 Initial value SADR7L is a special function register (SFR) used to store SA-ADC conversion results on channel 7.
Page 426: Sa-Adc Result Register 8L (Sadr8L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.18 SA-ADC Result Register 8L (SADR8L) Address: 0F2E0H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR8L SAR83 SAR82 Initial value SADR8L is a special function register (SFR) used to store SA-ADC conversion results on channel 0.
Page 427: Sa-Adc Result Register 9L (Sadr9L)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.20 SA-ADC Result Register 9L (SADR9L) Address: 0F2E2H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADR9L SAR93 SAR92 Initial value SADR9L is a special function register (SFR) used to store SA-ADC conversion results on channel 9.
Page 428: Sa-Adc Result Register Al (Sadral)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.22 SA-ADC Result Register AL (SADRAL) Address: 0F2E4H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADRAL SARA3 SARA2 Initial value SADRAL is a special function register (SFR) used to store SA-ADC conversion results on channel A.
Page 429: Sa-Adc Result Register Bl (Sadrbl)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.24 SA-ADC Result Register BL (SADRBL) Address: 0F2E6H Access: R Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADRBL SARB3 SARB2 Initial value SADRBL is a special function register (SFR) used to store SA-ADC conversion results on channel B.
Page 430: Sa-Adc Control Register 0 (Sadcon0)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.26 SA-ADC Control Register 0 (SADCON0) Address: 0F2F0H Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADCON0 SALP Initial value SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC.
Page 431: Sa-Adc Control Register 1 (Sadcon1)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.27 SA-ADC Control Register 1 (SADCON1) Address: 0F2F1H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SADCON1 SARUN Initial value SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC.
Page 432: Sa-Adc Mode Register 0 (Sadmod0)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.28 SA-ADC Mode Register 0 (SADMOD0) Address: 0F2F2H Access: R/W Access size: 8/16 bits Initial value: 00H SADMOD0 SACH7 SACH6 SACH5 SACH4 SACH3 SACH2 SACH1 SACH0 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s).
Page 433 ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) • SACH6 (bit 6) SACH6 Description Stops conversion on channel 6. (Initial value) Performs conversion on channel 6. • SACH7 (bit 7) SACH7 Description Stops conversion on channel 7. (Initial value) Performs conversion on channel 7.
Page 434: Sa-Adc Mode Register 1 (Sadmod1)
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.2.37 SA-ADC Mode Register 1 (SADMOD1) Address: 0F2F3H Access: R/W Access size: 8/16 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ SADMOD0 SACHB SACHA SACH9 SACH8 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s).
Page 435 ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.3 Description of Operation 26.3.1 Setup of the A/D conversion channel By setup of the SA-ADC mode register 0 (SADMOD0), as shown in the following table, A/D conversion operation is performed, and the A/D conversion result is stored in the SA-ADC result register.
Page 436: Operation Of Successive Approximation Type A/D Converter
ML610Q174 User’s Manual Chapter 26 Successive Approximation Type A/D Converter (SA-ADC) 26.3.2 Operation of Successive Approximation Type A/D Converter Use the following procedure to operate the SA-ADC: 1. Before starting the SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillation stabilizes.
Page 437: Battery Level Detector
Chapter 27 Battery Level Detector...
Page 438: Overview
ML610Q174 User’s Manual Chapter 27 Battery Level Detector Battery Level Detector 27.1 Overview This LSI includes a Battery Level Detector (BLD). 4 levels of threshold voltages can be selected by setting Battery Level Detector control register 0 (BLDCON0). 27.1.1 Features •...
Page 439: Description Of Registers
ML610Q174 User’s Manual Chapter 27 Battery Level Detector 27.2 Description of Registers 27.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Battery Level Detector control register 0F0D0H BLDCON0 8/16 BLDCON Battery Level Detector control register 0F0D1H...
Page 440: Battery Level Detector Control Register 0 (Bldcon0)
ML610Q174 User’s Manual Chapter 27 Battery Level Detector 27.2.2 Battery Level Detector Control Register 0 (BLDCON0) Address: 0F0D0H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ BLDCON0 Initial value BLDCON0 is a special function register (SFR) to control the Battery Level Detector [Description of Bits] •...
Page 441: Battery Level Detector Control Register 1 (Bldcon1)
ML610Q174 User’s Manual Chapter 27 Battery Level Detector 27.2.3 Battery Level Detector Control Register 1 (BLDCON1) Address: 0F0D1H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BLDCON1 BLDF ENBL Initial value BLDCON1 is a special function register (SFR) to control the Battery Level Detector.
Page 442: Description Of Operation
ML610Q174 User’s Manual Chapter 27 Battery Level Detector 27.3 Description of Operation 27.3.1 Threshold Voltage The threshold voltage (V ) is selected by setting the bits of BLDCON0. Table 27-1 shows the threshold voltages and the accuracy. Table 27-1 Threshold Voltages and Accuracy...
Page 443: Operation Of Battery Level Detector
ML610Q174 User’s Manual Chapter 27 Battery Level Detector 27.3.2 Operation of Battery Level Detector Activation (ON) and deactivation (OFF) of the Battery Level Detector are controlled by setting the ENBL bit of the Battery Level Detector control register (BLDCON1), and the result of the comparison of the power supply voltage ) to the threshold voltage is output to the BLDF bit of BLDCON1.
Page 444: Analog Comparator
Chapter 28 Analog Comparator...
Page 445: Overview
ML610Q174 User’s Manual Chapter 28 Analog Comparator Analog Comparator 28.1 Overview This LSI has two channel analog comparator, can compare the voltages supplied to two input pins (CMPnP and CMPnM). n=0,1 28.1.1 Features • The comparator output can generate an interrupt.
Page 446: List Of Pins
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.1.3 List of Pins Pin name Description P46/AIN6/ Input/output port, analog comparator inverted input pin CMP0M P52/ Input/output port, analog comparator non-inverted input pin CMP0P P47/AIN7/ Input/output port, analog comparator inverted input pin...
Page 447: Comparator0 Control Register 0 (Cmp0Con0)
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.2.2 Comparator0 Control Register 0 (CMP0CON0) Address: 0F950H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CMP0CON0 CMP0D CMP0EN Initial value CMP0CON0 is a special function register (SFR) to control the Comparator0.
Page 448: Comparator0 Control Registers 1 (Cmp0Con1)
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.2.3 Comparator0 Control Registers 1 (CMP0CON1) Address: 0F951H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ CMP0CON1 CMP0SM0 CMP0E1 CMP0E0 Initial value CMP0CON1 is special function registers (SFRs) to select the interrupt mode of Comparator0.
Page 449: Comparator1 Control Register 0 (Cmp1Con0)
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.2.4 Comparator1 Control Register 0 (CMP1CON0) Address: 0F954H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CMP1CON0 CMP1D CMP1EN Initial value CMP1CON0 is a special function register (SFR) to control the Comparator1.
Page 450: Comparator0 Control Registers 1 (Cmp1Con1)
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.2.5 Comparator0 Control Registers 1 (CMP1CON1) Address: 0F955H Access: R/W Access size: 8 bits Initial value: 00H ⎯ ⎯ ⎯ ⎯ ⎯ CMP1CON1 CMP1SM0 CMP1E1 CMP1E0 Initial value CMP1CON1 is special function registers (SFRs) to select the interrupt mode of Comparator1.
Page 451: Description Of Operation
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.3 Description of Operation 28.3.1 Analog Comparator Function The comparator can compare the voltages at CMPnP pin to the voltage at CMPnM pin, the output is shown in the CMPnD bit of comparator control register 0 (CMPnCON0).
Page 452: Interrupt Request
ML610Q174 User’s Manual Chapter 28 Analog Comparator 28.3.2 Interrupt Request When the interrupt edge chosen by the comparator control register 1 (CMPnCON1) occurs, a comparator interrupt (CMPnINT) occurs.The comparator interruption can perform selection of edge. Figure 28-3 shows the interrupt generation timing in rising-edge interrupt mode, in falling-edge interrupt mode, and in both-edge interrupt mode without sampling and the interrupt generation timing in rising-edge interrupt mode with sampling.
Page 453: Power Supply Circuit
Chapter 29 Power Supply Circuit...
Page 454: Overview
ML610Q174 User’s Manual Chapter 29 Power Supply Circuit Power Supply Circuit 29.1 Overview This LSI incorporates a regulated power supply circuit for the internal logic (VRL). The VRL outputs the operating voltage, V , for the internal logic, program memory, RAM, etc.
Page 455: Description Of Operation
ML610Q174 User’s Manual Chapter 29 Power Supply Circuit 29.2 Description of Operation voltage is set to about 2.1v in all the operational modes after a power supply injection. Figure 29-2 shows the operation waveforms of the power supply circuit. RESET_N pin...
Page 456: Flash Memory Programming
Chapter 30 Flash Memory Programming...
Page 457: Overview
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30. Flash Memory Programming 30.1 Overview This LSI has ISP (In System Programming) function that allows self-programming using a special function register (SFR) and remapping the boot area. 30.1.1 Features The flash memory rewrite function has the following features: •...
Page 458: Description Of Registers
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2 Description of Registers 30.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F0E0H Flash address register L FLASHAL 8/16 FLASHA 0F0E1H Flash address register H FLASHAH 0F0E2H...
Page 459: Flash Address Register L,H (Flashal,H)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.2 Flash Address Register L,H (FLASHAL,H) Address: 0F0E0H Access: R/W Access size: 8 bits/16 bits Initial value: 00H FLASHAL Initial value Address: 0F0E1H Access: R/W Access size: 8 bits/16 bits Initial value: 00H...
Page 460 ML610Q174 User’s Manual Chapter 30 Flash Memory Programming Table 30-1 Address Setting Values for Block Erase Area for block erase FLASHSEG FLASHAH Segment Address SEG1 SEG0 0:0000H 0:3FFFH Segment 0 0:4000H 0:7FFFH 0:8000H 0:BFFFH 0:0000H 0:3FFFH 0:4000H 0:7FFFH Segment 1...
Page 461: Flash Data Register L,H (Flashdl,H)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.3 Flash Data Register L,H (FLASHDL,H) Address: 0F0E2H Access: R/W Access size: 8 bits/16 bits Initial value: 00H FLASHDL Initial value Address: 0F0E3H Access: R/W Access size: 8 bits/16 bits Initial value: 00H...
Page 462: Flash Control Register (Flashcon)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.4 Flash Control Register (FLASHCON) Address: 0F0E4H Access: W Access size: 8 bits Initial value: 00H FLASHCON — — — — — — FSERS FERS Initial value FLASHCON is a write-only special function register (SFR) to control the block erase or the sector erase for the flash memory rewrite.
Page 463: Flash Acceptor (Flashacp)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.5 Flash Acceptor (FLASHACP) Address: 0F0E5H Access: W Access size: 8 bits Initial value: 00H FLASHACP fac7 fac6 fac5 fac4 fac3 fac2 fac1 fac0 Initial value FLASHACP is a write-only special function register (SFR) to control the block erase and the sector erase for the flash memory rewrite or enable/disable the 1-word write operation.
Page 464: Flash Self Register (Flashslf)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.7 Flash Self Register (FLASHSLF) Address: 0F0E7H Access: R/W Access size: 8 bits Initial value: 00H FLASHSLF — — — — — — — FSELF Initial value FLASHSLF is a special function register (SFR) for controlling the flash memory self-programming function.
Page 465: Flash Remap Register (Remapadd)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.2.8 Flash Remap Register (REMAPADD) Address: 0F0ECH Access: R/W Access size: 8 bits Initial value: 00H RBTA RES2 RES1 RES0 REA15 REA14 REA13 REA12 REMAPADD Initial value FLASHRMP is a special function register (SFR) which specify remap areas.
Page 466: Description Of Operation
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3 Description of Operation When using the flash memory rewrite function, prepare the program for rewrite in advance on a program code area with addresses that are not used for block erase or 1-word write.
Page 467 ML610Q174 User’s Manual Chapter 30 Flash Memory Programming Note when debugging the Flash self-write programming codes under U8 development environments, described in the following list. Table 30-4 Notes when debugging the Flash self-write programming codes Use case Notes • Do not have Real-time execution (GO execution) with any break points...
Page 468: Block Erase Function
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.1 Block Erase Function This function erases the flash memory data by block . (16K bytes). Write “0FAH” and “0F5H” to the flash acceptor (FLASHACP) and set the block address in the flash segment register and the flash address register H (FLASHAH).
Page 469: Sector Erase Function
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.2 Sector Erase Function This function erases the flash memory data by sector. (2K bytes). Write “0FAH” and “0F5H” to the flash acceptor (FLASHACP) and set the sector address in the flash segment register and the flash address register H (FLASHAH).
Page 470: 1-Word Write Function
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.3 1-word Write Function This function writes data to the flash memory by 1 word (2 bytes). Write “0FAH” and “0F5H” to the flash acceptor (FLASHACP) and set the address in the flash segment register (FLASHSEG) and the flash address register L, H (FLASHAL,H).
Page 471: Remap Function By Software
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.4 Remap function by software An address area 0000H~0FFFH (4KB) can be remapped to the same size 4KB of area starting with an address specified into REMAPADD register. Program codes start from the remapped area, by setting the FLSHRMP resiter and performing software reset (*only CPU is reset) with BRK instruction.
Page 472: Remap Function By Hardware (External Terminal)
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.5 Remap function by hardware (external terminal) When the power on reset or reset by a RESET_N port is released on the condition an external terminal (TEST0 pin) is set to High, 1KB of the ISP boot area (0:FC00H-0:FFFFH) is remapped to 0:0000H - 0:03FF and the program code starts running from the address FC00H Therefore, following two functions are available by programming a boot program in advance with LAPIS SEMI’s on-chip debug emulator uEASE.
Page 473: Notes In Use
ML610Q174 User’s Manual Chapter 30 Flash Memory Programming 30.3.6 Notes in Use • Be sure to write ”0FFH” to the unused area and the test area of the flash memory. If data in these areas is uncertain or not ”0FFH”, the operation cannot be guaranteed. For details, see Chapter 2, “CPU and Memory Space”.
Page 474: On-Chip Debug Function
Chapter 31 On-Chip Debug Function...
Page 475: Overview
ML610Q174 User’s Manual Chapter 31 On-Chip Debug Function On-Chip Debug Function 31.1 Overview This LSI has an on-chip debug function that enables flash memory reprogramming. To use the on-chip debug function, connect the LSI to the on-chip debug emulator (uEASE).
Page 476: Code-Option
Chapter 32 Code-Option...
Page 477: Overview
ML610Q174 User’s Manual Chapter 32 Code-Option Code-Option 32.1 Overview This LSI includes Code-option function. Used or unused of an 32.768kHz crystal oscillation can be selected as a low-speed clock, and with the code-option data written in the test data domain of the program memory. 8.192MHz or 8MHz can be selected as built-in PLL oscillating frequency by the code-option data.
Page 478: Description Of Registers
ML610Q174 User’s Manual Chapter 32 Code-Option 32.2 Description of Registers 32.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ ⎯* 0F3D8H Code-option register CODEOP0 * The contents of the Code-Option register 0 are dependent on the Code-Option data written in the test data domain of the program memory.
Page 479: Code-Option Register (Codeop0)
ML610Q174 User’s Manual Chapter 32 Code-Option 32.2.2 Code-Option Register (CODEOP0) Address: 0F3D8H Access: R/W Access size: 8 bits Initial value: 00H ―* ―* ―* ―* ―* ―* CODEOP0 COLOSC COPLL Initial value CODEOP0 is a special function register by which the set-up code-option data can be read. CODEOP0 can be read and writing is impossible.
Page 480: The Method Of A Setup Of Code-Option Data
ML610Q174 User’s Manual Chapter 32 Code-Option 32.3 The method of a setup of Code-Option data 32.3.1 The format of Code-Option data Set Code-Option data as 0：FDE0H address which is a test data domain of a program memory. ―* ―* ―* ―*...
Page 481: Appendixes
Appendixes...
Page 482: Appendix A Registers
ML610Q174 User’s Manual Appendix A Registers Appendix A Registers Contents of Registers Address Name Symbol Symbol size initial (Byte) (Word) value － 0F000H Data segment register － 0F001H Reset status register RSTAT Undefined 0F002H Frequency control register 0 FCON0 8/16...
Page 483 ML610Q174 User’s Manual Appendix A Registers 0F033H Timer 0 control register 1 TM0CON1 0F034H Timer 1 data register TM1D 8/16 0FFH TM1DC 0F035H Timer 1 counter register TM1C 0F036H Timer 1 control register 0 TM1CON0 8/16 TM1CON 0F037H Timer 1 control register 1 TM1CON1 －...
Page 484 ML610Q174 User’s Manual Appendix A Registers － 0F122H Display register 22 DSPR22 Undefined － 0F123H Display register 23 DSPR23 Undefined － 0F124H Display register 24 DSPR24 Undefined － 0F125H Display register 25 DSPR25 Undefined － 0F126H Display register 26 DSPR26 Undefined －...
Page 485 ML610Q174 User’s Manual Appendix A Registers － 0F269H Port D direction register PDDIR 0F26AH Port D control register 0 PDCON0 8/16 PDCON 0F26BH Port D control register 1 PDCON1 － 0F278H Port F data register － 0F279H Port F direction register...
Page 486 ML610Q174 User’s Manual Appendix A Registers 0F2D8H SA-ADC result register 4L SADR4L 8/16 SADR4 0F2D9H SA-ADC result register 4H SADR4H 0F2DAH SA-ADC result register 5L SADR5L 8/16 SADR5 0F2DBH SA-ADC result register 5H SADR5H 0F2DCH SA-ADC result register 6L SADR6L...
Page 487 ML610Q174 User’s Manual Appendix A Registers 0F8C7H PWM6 control register 1 PW6CON1 － 0F8C8H PWM6 control register 2 PW6CON2 0F8E0H Timer 8 data register TM8D 8/16 0FFH TM8DC 0F8E1H Timer 8 counter register TM8C 0F8E2H Timer 8 control register 0...
Page 488 Appendix B Package Dimensions Product name：ML610Q174-XXXGAZWAAL) Note that the package dimension is different from the "ML610Q174-xxxGAZWAX ". Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Page 489 Package Dimensions Product name：ML610Q174-NNNGAZWAX Note that the package dimension is different from the "ML610Q174-xxxGAZWAAL". Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Page 490: Appendix C Electrical Characteristics
ML610Q174 User’s Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics Absolute Maximum Ratings = 0V) Parameter Symbol Condition Rating Unit −0.3 to +7.0 Power supply voltage 1 Ta = 25°C −0.3 to +3.6 Power supply voltage 2 Ta = 25°C −0.3 to +2.33...
Page 491 ML610Q174 User’s Manual Appendix C Electrical Characteristics Operating Conditions of Flash Memory = 0V) Parameter Symbol Condition Range Unit Data flash memory, At write/erase -40 to +85 °C Operating temperature Flash ROM, At write/erase 0 to +40 Operating voltage At write/erase 2.2 to 5.5...
Page 492 ML610Q174 User’s Manual Appendix C Electrical Characteristics DC Characteristics (2 of 7) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Meas Parameter Symbol Condition Min. Typ. Max. Unit uring circuit LD3 to 0 = 0H 2.35 BLD threshold LD3 to 0 = 3H Typ.
Page 493 ML610Q174 User’s Manual Appendix C Electrical Characteristics DC Characteristics (6 of 7) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Output voltage 1 (P20 to P23) IOH1 = −0.5mA VOH1 ―...
Page 494 ML610Q174 User’s Manual Appendix C Electrical Characteristics DC Characteristics (7 of 7) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Input voltage 1 (RESET_N) 0.7× (TEST0) VIH1 ―...
Page 495 ML610Q174 User’s Manual Appendix C Electrical Characteristics Measuring circuit Measuring Circuit 1 32.768kHz crystal OSC0 OSC1 8MHz crystal ：10μF ：10μF ：12pF ：12pF ：47pF ：47pF ：0.22μF 32.768kHz Crystal oscillator (DMX-26 DAISHINKU Corp.) 8MHz Crystal oscillator CSTLS8M00G56 （MURATA Corp.） it has built-in C...
Page 496 ML610Q174 User’s Manual Appendix C Electrical Characteristics Measuring Circuit 3 (*1) (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. Measuring Circuit 4 (*3) *3: Measured at the specified input pins. Measuring Circuit 5 (*1) *1: Input logic circuit to determine the specified measuring conditions.
Page 497 ML610Q174 User’s Manual Appendix C Electrical Characteristics AC Characteristics (External Interrupt) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit External interrupt disable Interrupt: Enabled (MIE = 1), 2.5× 3.5× μs ―...
Page 498 ML610Q174 User’s Manual Appendix C Electrical Characteristics AC Characteristics (Synchronous Serial Port) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit μs High-speed oscillation stopped ― ― SCK input cycle SCYC...
Page 499 ML610Q174 User’s Manual Appendix C Electrical Characteristics AC Characteristics (I C bus interface : Standard mode 100kHz) =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. ⎯ ⎯ SCL clock frequency SCL hold time ⎯...
Page 500 ML610Q174 User’s Manual Appendix C Electrical Characteristics Electrical Characteristics of Successive Approximation Type A/D Converter =2.2 to 5.5V, V =0V, Ta=−40 to +85°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Resolution ― ― ― bits 2.7V ≤ V ≤...
Page 501 ML610Q174 User’s Manual Appendix C Electrical Characteristics Power-on/Shutdown Sequence When the power rise time is 100 μs or less Upon shutdown Upon power-on 100μs(min.) RESET_N When the power rise time is more than 100 μs Upon shutdown Upon power-on 2.0V...
Page 502: Appendix D The Example Of An Application Circuit
ML610Q174 User’s Manual Appendix D The example of an application circuit Appendix D The example of an application circuit 5.0V uEASE COM0~3 SEG0~23, UVDD_O RESET_N TEST1_N P85/V TEST TEST0 P84V ML610Q174 RESET_N Reset-IC PF5/PWM5 (Output) IGBT control PF4/PWM4 (Output) 32.768KHz...
Page 503: Appendix E Check List
[ ] For fail safe in your system, please fill unused program memory area (your program code does not use) with BRK instruction code “0FFH”. Please fill the area with the code “0FFH” when you release a code for LAPIS Semiconductor’s factory programming.
Page 504 ML610Q174 User’s Manual Appendix D Appendix E Check List Chapter 6 Clock Generation Circuit •Initial System clock [ ] At power up or system reset, the 16MHz PLLl oscillation clock oscillates and 2MHz clock which is 1/8 of 16MHz is supplied to CPU as the system clock.
Page 505 [ ] Please do not apply LSIs being used for debugging to mass production. [ ] Please validate the ROM code on your production board without LAPIS semiconductor development tool uEASE. Chapter 32 Code-Option [ ] Set Code-option data as the test data domain of a program memory.
Page 506: Revision History
Revision History...
Page 507 Aug 31, 2018 -Added the note that the package dimension is different each other between the two product names. -Added description of product name (ML610Q174-xxxGAZWAAL) to the package dimension. -Added description of product name (ML610Q174-xxxGAZWAX) to the package dimension. FEUL610Q174...

LAPIS Semiconductor ML610Q174 User Manual

Chapter 1 Overview

Chapter 2 CPU and Memory Space

Chapter 3 Reset Function

Chapter 4 MCU Control Function

Chapter 5 Interrupts (Ints)

Chapter 6 Clock Generation Circuit

Chapter 7 Time Base Counter

Chapter 8 Timers

Chapter 9 Watchdog Timer

Chapter 10 PWM

Chapter 11 Synchronous Serial Port

Chapter 12 UART

Chapter 13 I 2 C Bus Interface

Chapter 14 Port 0

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