LAPIS Semiconductor ML62Q1000 Series User Manual page 705

Table 23-4 A/D conversion time when using the internal reference voltage as reference voltage
SADMOD
SASHT[3:0]
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
[Note]
Ÿ
If choosing to start A/D conversion after discharging the internal sample hold capacitive electrical
charge to the VSS level at the start of A/D conversion, the A/D conversion time shown in Table 23-3 and
23-4 is increased by two clocks of the conversion clock (SAD_CLK).
Ÿ
The A/D conversion time does not include the clock frequency error.
SADMOD
SASHT[3:0]
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
FEUL62Q1000
Conversion
clock count
0 0 14
0 1 15
1 0 16
1 1 17
0 0 18
0 1 19
1 0 20
1 1 21
0 0 29
0 1 45
1 0 61
1 1 77
0 0 93
0 1 109
1 0 125
1 1 141
Table 23-5 Sampling time when using V
Sample/
hold
clock count
0 0 1
0 1 2
1 0 3
1 1 4
0 0 5
0 1 6
1 0 7
1 1 8
0 0 16
0 1 32
1 0 48
1 1 64
0 0 80
0 1 96
1 0 112
1 1 128
Chapter 23 Successive Approximation Type A/D Converter
32kHz 0.5MHz
427 μs
Prohibited
58 μs
Prohibited
90 μs
122 μs
154 μs
186 μs
218 μs
250 μs
282 μs
or V
DD REF
32kHz 0.5MHz
30 μs 2 μs
4 μs
6 μs
8 μs
10 μs
12 μs
14 μs
16 μs
32 μs
Prohibited
64 μs
96 μs
128 μs
160 μs
192 μs
224 μs
256 μs
ML62Q1000 Series User's Manual
Conversion time
SAD_CLK
1MHz 2MHz
Prohibited
Prohibited
45 μs
61 μs
77 μs 38.5 μs
93 μs 46.5 μs
109 μs 54.5 μs
125 μs 62.5 μs
141 μs 70.5 μs
pin as reference voltage
Sampling time
SAD_CLK
1MHz 2MHz
Prohibited
Prohibited
2 μs
3 μs 1.5 μs
4 μs 2 μs
5 μs 2.5 μs
6 μs 3 μs
7 μs 3.5 μs
8 μs 4 μs
16 μs 8 μs
32 μs 16 μs
48 μs 24 μs
64 μs 32 μs
80 μs 40 μs
96 μs 48 μs
112 μs 56 μs
128 μs 64 μs
4MHz 8MHz
Prohibited
Prohibited
35.25 μs
4MHz 8MHz
Prohibited
Prohibited
1 μs
1.25 μs 0.625 μs
1.5 μs 0.75 μs
1.75 μs 0.875 μs
2 μs 1 μs
4 μs 2 μs
8 μs 4 μs
12 μs 6 μs
16 μs 8 μs
20 μs 10 μs
24 μs 12 μs
28 μs 14 μs
32 μs 16 μs
23-29