LAPIS Semiconductor ML62Q1000 Series User Manual page 863

See Section 4.3.8 "Block Control Function".
[ ] If the clock supply is only stopped without resetting each peripheral circuit using the block control
function, it may cause the output levels of the timer, communication and buzzer pins to be fixed, causing
the excess current to flow. Also, in the successive approximation type A/D converter, D/A converter and
analog comparator, the circuits may stop their function with the current kept flowing. Therefore, make
sure to stop the clock with the reset established using the BRECONn register.
Chapter 5 Interrupts
See Section 5.2.10 "Interrupt Level Control Enable Register (ILEN)".
[ ] If peripheral circuits need to work in the HALT-H mode, choose the low-speed clock for the operating
clock.
[ ] Enable the interrupt level control function by setting the ILE bit to "1" when the interrupt is disabled(IE0
to IE7 registers are "0") or master interrupt enable flag(MIE) is "0", otherwise, an interrupt may occur with
an unexpected interrupt level.
See Section 5.2.12 "Interrupt Level Control Register 0 (ILC0)".
[ ] Write to this register when the interrupt is disabled (IE0 to IE7 registers are "0x00") or the master
interrupt enable flag (MIE) is "0", otherwise, an interrupt may occur with an unexpected interrupt level.
See Section 5.3 "Description of Operation".
[ ] The watchdog timer interrupt (WDTINT) is a non-maskable interrupt. If the non-maskable interrupt
occurs while an interrupt processing is in progress, abort the interrupt processing and proceed with
processing the non-maskable interrupt preferentially regardless of multiple interrupts enabled/disabled.
[ ] For failsafe, define unused all interrupt vectors. If an unused interrupt occurs, it may indicate the
possibility that the CPU went out of control. It is recommended to cause the watch dog timer (WDT) reset
to occur using the infinite loop to initialize the LSI.
See Section 5.3.4 "Notes on Interrupt Routine (with Interrupt Level Control Disabled)".
[ ] Do not enable interrupts in a subroutine called from an interrupt routine for which multiple interrupts are
disabled. Otherwise, the program may run out of control when multiple interrupts occur.
[ ] Writing "0" to the ILE bit of the interrupt level control enable register (ILEN) causes the interrupt level
control to be disabled.
See Section 5.3.5 "Flow Charts When Interrupt Level Control Is Enabled".
[ ] For processing of non-maskable interrupt, follow the flow chart "When multiple interrupts are enabled".
Registers that should be saved in the stack are ELR2 and EPSW2.
[ ] When programming in C, it is not required to write program codes for saving/restoring registers
because they are generated in the C compiler. However, program codes for enabling/disabling interrupts
through EI and DI instructions and for writing to the current interrupt request level register (CIL) must be
written. See Section 5.3.6 "How To Write Interrupt Processing When Interrupt Level Control Enabled" for
the specific program description.
See Section 5.3.6.1 "Description of Interrupt Function to Disable Multiple Interrupts".
[ ] Do not enable interrupts in a function called from a function for which multiple interrupts are disabled.
Otherwise, the program may run out of control when the multiple interrupts occur.
Chapter 6 Clock Generation Circuit
See Section 6.1.2 "Configuration".
[ ] After the power-on or the system reset, the low-speed RC oscillation clock (32.768 kHz) is initially
chosen and supplied to the system clock (SYSTEMCLK).
See Section 6.2.2 "High-Speed Clock Mode Register (FHCKMOD)".
[ ] When the voltage of VDD is 1.6V≦VDD＜1.8V, set the system clock to 4 MHz or lower. If it exceeds
4MHz, the operation is not guaranteed.
[ ] For output of the high-speed clock (OUTHSCLK), the output clock frequency is limited according to the
voltage of VDD.
1.6V≦VDD＜1.8V : Choose 4 MHz or lower
1.8V≦VDD≦5.5V : Choose 12 MHz or lower
FEUL62Q1000
ML62Q1000 Series User's Manual
Appendix E. List of Notes
E-4