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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 1 Overview
1.2 Configuration of Functional Blocks
1.2.1 Block Diagram of ML610471/ML610472/ML610473
EPSW1−3
Controller
Flash
Writer
V
DD
V
SS
RESET_N
RESET &
TEST0
TEST
XT0
XT1
OSC
LSCLK*
Power
V
DDL
RC-ADC
×1
RCM*
IN1*
CS1*
RS1*
RT1*
Secondary function or Tertiary function
*
(*1) Select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons with the register
(*2) Select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons with the register
(*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons with the register
CPU (nX-U8/100)
GREG
0−15
PSW
Timing
ALU
Instruction
Decoder
INT
1
INT
4
INT
1
INT
2
Figure 1-1 Block Diagram of ML610471/ML610472/ML610473
ELR1−3
ECSR1−3
LR
DSR/CSR
EA
PC
SP
BUS
Instruction
Controller
Register
Data-bus
RAM
512 byte
Interrupt
Controller
WDT
TBC
Capture
×2
8bit Timer
×2
Display
register
110bit
1-4
Program
Memory
(Mask)
8Kbyte
INT
1
RXD0*
UART
TXD0*
INT
5
P00 to P03
P20, P21
P35
GPIO
P42 to P47
P60 to P67 (ML610471)
P60 to P63 (ML610472)
COM0 to COM4 (*1)(*2)(*3)
LCD
Driver
SEG0 to SEG13 (ML610471) (*1)
SEG0 to SEG17 (ML610472) (*2)
SEG0 to SEG21 (ML610473) (*3)
V
LCD
L1
BIAS
C1, C2
, V
, V
L2
L3
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