LAPIS Semiconductor ML62Q1000 Series User Manual page 377

9.3.7.3 Emergency Stop Operation
Writing "1" to the FTnEMGEN bit of the FTCCON register causes the emergency stop function to be enabled. Set the
FTnEMGEN bit after the trigger source is chosen in the FTnEST bit of the FTnTRG0 register.
If the emergency stop trigger input (rising edge) is present, the counter is stopped, brings Positive/Negative phase output
to "L" level, and generates an emergency stop interrupt.
To restart the counter operation, write "1" to the FTnICES bit of the FTnINTC register to clear the emergency stop
interrupt status.
Figure 9-17 shows the operation timing at emergency stop.
Emergency stop trigger
Event trigger
FTnRUN
FTnISES
Positive/Negative
phase
FTnC
(1) The counter operation starts by the event trigger (falling edge).
(2) The counter stops at by the emergency stop trigger (rising edge). The emergency stop interrupt occurs.
(3) The event trigger is disabled due to the emergency stop in progress.
(4) Clear the emergency stop interrupt to enable the operation.
(5) The counter operation restarts by the event trigger (falling edge).
(The counter is not cleared in this example, so pulse output is restarted after one cycle)
Once the emergency stop occurs, the counter is stopped after one clock of the timer clock, and the FTnISES bit of the
FTnINTS register becomes "1" (see (2) in Figure 9-17).
When the FTnISES bit is "1", even if the event trigger of counter start is generated, it is not accepted. If the event trigger
for the counter start is generated after the FTnISES bit is cleared (see (4) in Figure 9-17), counting up is restarted (see (5)
in Figure 9-17).
To restart the counting operation by the software, make sure that the the FTnISES bit becomes "0".
FEUL62Q1000
(1)
0000 Count up 0000
Figure 9-17 Operation Timing Diagram at Emergency Stop
(2) (3) (4)
Counting stopped
Count up
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
(5)
Count up 0000 Count up
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