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In the state where clock supply to each peripheral circuit is suspended or in the reset state, writing to SFRs of
corresponding peripheral circuits is disabled. The initial values are read for reading the SFRs of peripheral circuits.
[Note]
Ÿ
If the clock supply is only stopped without resetting each peripheral circuit using the block control
function, it may cause the output levels of the timer, communication and buzzer pins to be fixed, causing
the excess current to flow. Also, in the successive approximation type A/D converter, D/A converter and
analog comparator, the circuits may stop their function with the current kept flowing. Therefore, make
sure to stop the clock with the reset established using the BRECONn register.
Availability of the SFR bit symbols is dependent of the product specification.
Table 4-7 Availability of the SFR bit symbols in BCLCONn register and BRECONn register
Control register / bit
Word symbol
Bit symbol
BCKCON0
DCKTM0
DCKTM1
DCKTM2
DCKTM3
DCKTM4
DCKTM5
DCKTM6
DCKTM7
BCKCON1
DCKFTM0
DCKFTM1
DCKFTM2
DCKFTM3
DCKFTM4
DCKFTM5
DCKFTM6
DCKFTM7
DCKI2CM0
DCKI2CM1
DCKI2CU0
BCKCON2
DCKSU0
DCKSU1
DCKSU2
DCKSU3
DCKSU4
DCKSU5
DCKCRC
DCKACC
DCKBUZ
DCKDMA
BCKCON3
DCKSAD
DCKDAC
DCKLCD
DCKDAC1
DCKCMP0
DCKCMP1
●
: Available
- : Unavailable
FEUL62Q1000
Word symbol
Bit symbol
BRECON0
RSETM0
RSETM1
RSETM2
RSETM3
RSETM4
RSETM5
RSETM6
RSETM7
BRECON1
RSEFTM0
RSEFTM1
RSEFTM2
RSEFTM3
RSEFTM4
RSEFTM5
RSEFTM6
RSEFTM7
RSEI2CM0
RSEI2CM1
RSEI2CU0
BRECON2
RSESU0
RSESU1
RSESU2
RSESU3
RSESU4
RSESU5
RSECRC
RSEACC
RSEBUZ
RSEDMA
BRECON3
RSESAD
RSEDAC
RSELCD
RSEDAC1
RSECMP0
RSECMP1
●
*1
: Available on ML62Q1700 group
ML62Q1000 Series User's Manual
Chapter 4 Power Management
Available / Unavailable
ML62Q1300
ML62Q1500 / ML62Q1700
group
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4-29
- Quick Links:
- Block Diagram of Ml62Q1300 Group
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