LAPIS Semiconductor ML62Q1000 Series User Manual page 479

12.3.1.5 Control Register Setting Wait State
Control register setting wait state start
Generate I
Confirm transmit error flag and
Load received data into CPU
Set communication mode
Control register setting wait state
completed (move to one of: data
transmission/reception mode, stop
condition, or restart condition)
12.3.1.6 Data Transmission Mode
Data transmit mode start
Transmit value of I
data register (I2UM0TD)
Acknowledgment signal is received by
the I
Data transmit mode completed
FEUL62Q1000
2
C bus unit 0 interrupt
(I2CU0INT)
acknowledgment data
Write transmitted data
Set control register
2
C bus 0 transmit
2
C bus status register
(move to control register
setting wait state)
ML62Q1000 Series User's Manual
When entering the control register setting wait state,
an interrupt is generated through hardware
Confirm I2UM0ER and I2UM0ACR bits
in the I2UM0STA register
<Only when data is received> Read the I2UM0RD register
and load received data into the CPU
I2UM0R7 to I2UM0R0 bits: 8-bit receive data
<Only when data is transmitted> Set I2UM0TD register
I2UM0T7 to I2UM0T0 bits: 8-bit transmit data
<Only when operation mode is changed>
Set I2UM0MOD register
Set the I2UM0CON register
I2UM0ST bit: Starts communication (I2UM0ST=1)
I2UM0SP bit: Stop condition request (I2UM0SP=1)
I2UM0RS bit: Restart request (I2UM0RS=1)
Transmission data that has been written to the I2UM0TD
register is transmitted from the I2CU0_SDA pin in MSB first
I2UM0T7 to I2UM0T0 bits: 8-bit transmit data
Value transmitted from the I2CU0_SDA pin
is stored in the I2UM0RD register
Acknowledgment signal is received through hardware
I2UM0ACR bit: Acknowledgment data
2
I C bus 0 control register (I2UM0CON) setting wait state
Chapter 12 I2C Bus Unit
12-23