The interrupt request TMnINT generation cycle and the port output variation cycle can be expressed in the following
formula:
See Section 8.3.3.1 "Start/Stop Timing" for the timing of the timer start/stop and counting up. See Section 8.3.3.2
"External Input Count Timing" for the counting up timing when using the external input.
FEUL62Q1000
TMHnDH + 1
T
=
TMIH
THnCK (Hz)
TMHnDH
THnCK
TMHnDL + 1
T
=
TMIL
THnCK (Hz)
TMHnDL
THnCK
ML62Q1000 Series User's Manual
(n=0 to 7)
: TMHnDH register setting value (0x01 to 0xFF)
: Count clock frequency chosen in the TMHnMOD register
(n=0 to 7)
: TMHnDL register setting value (0x01 to 0xFF)
: Count clock frequency chosen in the TMHnMOD register
Chapter 8 16-Bit Timer
8-23