LAPIS Semiconductor ML62Q1000 Series User Manual page 14

21.2.5 D/A Converter 1 Code Register (DACCODE1) ........................................................................................ 21-9
21.3 Description of Operation ......................................................................................................................... 21-10
21.3.1 D/A Converter Operation ......................................................................................................................... 21-10
Chapter 22
22. Voltage Level Supervisor ............................................................................................................................. 22-1
22.1 General Description ................................................................................................................................... 22-1
22.1.1 Features ...................................................................................................................................................... 22-2
22.1.2 Configuration ............................................................................................................................................. 22-3
22.2 Description of Registers ............................................................................................................................. 22-4
22.2.1 List of Registers ......................................................................................................................................... 22-4
22.2.2 Voltage Level Supervisor 0 Control Register (VLS0CON) ....................................................................... 22-5
22.2.3 Voltage Level Supervisor 0 Mode Register (VLS0MOD)......................................................................... 22-6
22.2.4 Voltage Level Supervisor 0 Level Register (VLS0LV) ............................................................................. 22-8
22.2.5 Voltage Level Supervisor 0 Sampling Register (VLS0SMP) .................................................................... 22-9
22.3 Description of Operation ......................................................................................................................... 22-10
22.3.1 Supervisor Mode ...................................................................................................................................... 22-11
22.3.2 Single Mode ............................................................................................................................................. 22-16
Chapter 23
23. Successive Approximation Type A/D Converter .......................................................................................... 23-1
23.1 General Description ................................................................................................................................... 23-1
23.1.1 Features ...................................................................................................................................................... 23-2
23.1.2 Configuration ............................................................................................................................................. 23-3
23.1.3 List of Pins ................................................................................................................................................. 23-4
23.2 Description of Registers ............................................................................................................................. 23-6
23.2.1 List of Registers ......................................................................................................................................... 23-6
23.2.2 SA-ADC Result Register n (SADRn : n=0 to 15, 16)................................................................................ 23-8
23.2.3 SA-ADC Result Register (SADR) ............................................................................................................. 23-9
23.2.4 SA-ADC Upper/Lower Limit Status Register 0 (SADULS0) ................................................................. 23-10
23.2.5 SA-ADC Upper/Lower Limit Status Register 1 (SADULS1) ................................................................. 23-11
23.2.6 SA-ADC Mode Register (SADMOD) ..................................................................................................... 23-12
23.2.7 SA-ADC Control Register (SADCON) ................................................................................................... 23-13
23.2.8 SA-ADC Enable Register 0 (SADEN0) .................................................................................................. 23-14
23.2.9 SA-ADC Enable Register 1 (SADEN1) .................................................................................................. 23-15
23.2.10 SA-ADC Conversion Interval Setting Register (SADSTM) .................................................................. 23-16
23.2.11 SA-ADC Upper/Lower Limit Mode Register (SADLMOD) ................................................................ 23-17
23.2.12 SA-ADC Upper Limit Setting Register (SADUPL) .............................................................................. 23-18
23.2.13 SA-ADC Lower Limit Setting Register (SADLOL) ............................................................................. 23-18
23.2.14 SA-ADC Reference Voltage Control Register (VREFCON) ................................................................ 23-19
23.2.15 SA-ADC Interrupt Mode Register (SADIMOD) ................................................................................... 23-20
23.2.16 SA-ADC Trigger Register (SADTRG) .................................................................................................. 23-21
23.2.17 SA-ADC test mode register (SADTMOD) ............................................................................................ 23-22
23.3 Description of Operation ......................................................................................................................... 23-23
23.3.1 Operation of Successive Approximation Type A/D Converter ............................................................... 23-23
23.3.2 How to test the Successive Approximation Type A/D Converter............................................................ 23-27
23.3.3 A/D Conversion Time Setting ................................................................................................................. 23-28
23.4 Notes on SA-ADC ................................................................................................................................... 23-31
23.4.1 Sampling Time Setting ............................................................................................................................ 23-31
23.4.2 Noise Suppression ................................................................................................................................... 23-32
Chapter 24
24. Regulator....................................................................................................................................................... 24-1
24.1 General Description ............................................................................................................................... 24-1
24.1.1 Features ............................................................................................................................................. 24-1
24.1.2 Configuration .................................................................................................................................... 24-1
24.1.3 List of Pins ........................................................................................................................................ 24-2
FEUL62Q1000
ML62Q1000 Series User's Manual
Contents-9
Contents