LAPIS Semiconductor ML62Q1000 Series User Manual page 350

Bit symbol
Bit no.
name
1 FTnISA
0 FTnISP
FEUL62Q1000
This is a bit to indicate the state of the event timing A interrupt of FTMn.
In CAPTURE mode, it indicates the status of storing the capture data into the FTnEA register.
Ÿ TIMER, PWM1, PWM2 mode
0: Event timing A interrupt has not occurred (initial value)
1: Event timing A interrupt has occurred
This bit is cleared by writing "1" to FTnICA bit of FTnINTC register.
Ÿ CAPTURE mode
0: Capture A interrupt has not occurred
1: Capture A interrupt has occurred
This bit is cleared by writing "1" to FTnICA bit of FTnINTC register or by reading the
FTnEA register.
This is a bit to indicate the state of the cyclic interrupt of FTMn.
0: Cyclic interrupt has not occurred (initial value)
1: Cyclic interrupt has occurred
This bit is cleared by writing "1" to FTnICP bit of FTnINTC register.
ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
Description
9-30